RT

Rajesh Tiwari

TI Texas Instruments: 8 patents #1,843 of 12,488Top 15%
Motorola: 3 patents #3,303 of 12,470Top 30%
Oracle: 3 patents #4,017 of 14,854Top 30%
QU Qualcomm: 2 patents #5,578 of 12,104Top 50%
EN Entegris: 1 patents #376 of 643Top 60%
WE Webmd: 1 patents #11 of 31Top 40%
Overall (All Time): #251,394 of 4,157,543Top 7%
18
Patents All Time

Issued Patents All Time

Patent #TitleCo-InventorsDate
11635974 Providing a different configuration of added functionality for each of the stages of predeployment, deployment, and post deployment using a layer of abstraction Ariel Cohen, Javier Espeche, Jonathan Lopez Lopez 2023-04-25
11449348 Pre/post deployment customization Ariel Cohen, Javier Espeche, Jonathan Lopez Lopez 2022-09-20
11333707 Testing of integrated circuits during at-speed mode of operation Khushboo Agarwal, Sanjay Krishna Hulical Vijayaraghavachar, Raashid Moin Shaikh, Srivaths Ravi, Wilson Pradeep 2022-05-17
10521243 Pre/post deployment customization Ariel Cohen, Javier Espeche, Jonathan Lopez Lopez 2019-12-31
10471567 CMP pad conditioning assembly Patrick J. Doering, Andrew Galpin 2019-11-12
9972402 Continuous write and read operations for memories with latencies Nishi Bhushan Singh, Ashutosh Anand, Anand Bhat, Shankarnarayan Bhat 2018-05-15
9971663 Method and apparatus for multiple memory shared collar architecture Nishi Bhushan Singh, Anand Bhat, Ashutosh Anand, Abhinav Kothiala 2018-05-15
8856601 Scan compression architecture with bypassable scan chains for low test mode power Srivaths Ravi, Rubin Ajit Parekhji 2014-10-07
8618661 Die having coefficient of thermal expansion graded layer Brian K. Kirkpatrick 2013-12-31
8205125 Enhanced control in scan tests of integrated circuits with partitioned scan chains Alan Hales, Srujan Kumar Nakidi, Rubin Ajit Parekhji, Srivaths Ravi 2012-06-19
7519905 Automatic formatting and validating of text for a markup language graphical user interface Panagiotis Kougiouris, Chip Bering 2009-04-14
7387960 Dual depth trench termination method for improving Cu-based interconnect integrity Russell Fields, Scott A. Boddicker, Andrew Tae Kim 2008-06-17
7010381 Versatile system for controlling semiconductor topography Nital S. Patel 2006-03-07
6941242 Versatile system for variance-based data analysis Nital S. Patel 2005-09-06
6709974 Method of preventing seam defects in isolated lines David Permana, Jiong-Ping Lu, Albert Cheng, Jeff West, Brock W. Fairchild +3 more 2004-03-23
6573173 Method for forming a copper interconnect using a multi-platen chemical mechanical polishing (CMP) process János Farkas, Brian G. Anthony, Abbas Guvenilir, Mohammed Rabiul Islam, Venkat R. Kolagunta +2 more 2003-06-03
6444569 Method for forming a copper interconnect using a multi-platen chemical mechanical polishing (CMP) process János Farkas, Brian G. Anthony, Abbas Guvenilir, Mohammed Rabiul Islam, Venkat R. Kolagunta +2 more 2002-09-03
6274478 Method for forming a copper interconnect using a multi-platen chemical mechanical polishing (CMP) process János Farkas, Brian G. Anthony, Abbas Guvenilir, Mohammed Rabiul Islam, Venkat R. Kolagunta +2 more 2001-08-14