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Continuous write and read operations for memories with latencies |
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2018-05-15 |
| 9971663 |
Method and apparatus for multiple memory shared collar architecture |
Nishi Bhushan Singh, Ashutosh Anand, Rajesh Tiwari, Abhinav Kothiala |
2018-05-15 |
| 9711241 |
Method and apparatus for optimized memory test status detection and debug |
Ashutosh Anand, Shankarnarayan Bhat, Nikhil Sudhakaran, Praveen Raghuraman, Nishi Bhushan Singh +4 more |
2017-07-18 |
| 8749286 |
Programmable scannable storage circuit |
Pranjal Tiwari, Aishwarya Dubey, Naishad Narendra Parikh, Puneet Sabbarwal |
2014-06-10 |
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Methods, devices and software applications for facilitating a development of a computer program |
Manish Makkar |
2014-04-29 |
| 8479068 |
Decoded register outputs enabling test clock to selected asynchronous domains |
Pradeep Periasamy, Tamilselvi Natarajan |
2013-07-02 |
| 7373571 |
Achieving desired synchronization at sequential elements while testing integrated circuits using sequential scan techniques |
Yatin R. Acharya |
2008-05-13 |