Issued Patents All Time
Showing 1–25 of 33 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12313681 | Identifying defect sensitive codes for testing devices with input or output code | Lakshmanan Balasubramanian, Nadeem Husain Tehsildar, Suresh Mallala, Nitin Agarwal | 2025-05-27 |
| 11994559 | Tests for integrated circuit (IC) chips | Lakshmanan Balasubramanian, Kalyan Chakravarthi Chekuri, Swathi G | 2024-05-28 |
| 11921159 | Compressed scan chain diagnosis by internal chain observation, processes, circuits, devices and systems | Prakash Narayanan, Arvind Jain, Sundarrajan Subramanian | 2024-03-05 |
| 11592483 | Compressed scan chain diagnosis by internal chain observation, processes, circuits, devices and systems | Prakash Narayanan, Arvind Jain, Sundarrajan Subramanian | 2023-02-28 |
| 11320478 | Methods of testing multiple dies | Mahesh M. Mehendale, Vinod Menezes, Vipul Kumar Singhal | 2022-05-03 |
| 11119152 | Functional circuitry, decompressor circuitry, scan circuitry, masking circuitry, qualification circuitry | Prakash Narayanan, Arvind Jain, Sundarrajan Subramanian | 2021-09-14 |
| 10746797 | Dynamically protective scan data control | Mudasir Shafat Kawoosa | 2020-08-18 |
| 10684322 | Systems and methods of testing multiple dies | Mahesh M. Mehendale, Vinod Menezes, Vipul Kumar Singhal | 2020-06-16 |
| 10606723 | Systems and methods for optimal trim calibrations in integrated circuits | Pankaj Bongale, Partha Ghosh | 2020-03-31 |
| 10591540 | Compressed scan chains with three input mask gates and registers | Prakash Narayanan, Arvind Jain, Sundarrajan Subramanian | 2020-03-17 |
| 10180454 | Systems and methods of testing multiple dies | Mahesh M. Mehendale, Vinod Menezes, Vipul Kumar Singhal | 2019-01-15 |
| 9952283 | Compressed scan chains with three input mask gates and registers | Prakash Narayanan, Arvind Jain, Sundarrajan Subramanian | 2018-04-24 |
| 9581645 | Test circuit providing different levels of concurrency among radio cores | Adesh Sontakke, Rajesh Mittal, Upendra Narayan Tripathi | 2017-02-28 |
| 9263147 | Method and apparatus for concurrent test of flash memory cores | Rajat Mehrotra, Maheedhar Janaki Jalasutram, Charu Shrimali | 2016-02-16 |
| 9229055 | Decompressed scan chain masking circuit shift register with log2(n/n) cells | Prakash Narayanan, Arvind Jain, Sundarrajan Subramanian | 2016-01-05 |
| 9091729 | Scan chain masking qualification circuit shift register and bit-field decoders | Prakash Narayanan, Arvind Jain, Sundarrajan Subramanian | 2015-07-28 |
| 8972807 | Integrated circuits capable of generating test mode control signals for scan tests | Rajesh Mittal, Puneet Sabbarwal, Prakash Narayanan | 2015-03-03 |
| 8887018 | Masking circuit removing unknown bit from cell in scan chain | Prakash Narayanan, Arvind Jain, Sundarrajan Subramanian | 2014-11-11 |
| 8856601 | Scan compression architecture with bypassable scan chains for low test mode power | Srivaths Ravi, Rajesh Tiwari | 2014-10-07 |
| 8839063 | Circuits and methods for dynamic allocation of scan test resources | Srivaths Ravi, Prakash Narayanan, Milan Shetty | 2014-09-16 |
| 8799713 | Interruptible non-destructive run-time built-in self-test for field testing | Swathi Gangasani, Srinivasulu Alampally, Prohor Chowdhury, Srinivasa Chakravarthy, Padmini Sampath | 2014-08-05 |
| 8694276 | Built-in self-test methods, circuits and apparatus for concurrent test of RF modules with a dynamically configurable test structure | Adesh Sontakke, Rajesh Mittal, Upendra Narayan Tripathi | 2014-04-08 |
| 8671329 | Low overhead and timing improved architecture for performing error checking and correction for memories and buses in system-on-chips, and other circuits, systems and processes | Sanjay Kumar, Amit Kumar Dutta, Srivaths Ravi | 2014-03-11 |
| 8438437 | Structures and control processes for efficient generation of different test clocking sequences, controls and other test signals in scan designs with multiple partitions, and devices, systems and processes of making | Arvind Jain, Prashant Mohan Kulkarni, Srinivas Kumar Vooka, Sundarrajan Subramanian | 2013-05-07 |
| 8438344 | Low overhead and timing improved architecture for performing error checking and correction for memories and buses in system-on-chips, and other circuits, systems and processes | Sanjay Kumar, Amit Kumar Dutta, Srivaths Ravi | 2013-05-07 |