Issued Patents All Time
Showing 26–33 of 33 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8286042 | On-chip seed generation using boolean functions for LFSR re-seeding based logic BIST techniques for low cost field testability | Swathi Gangasani, Srinivasulu Alampally, Divya Divakaran, Amit Kumar Dutta, Srivaths Ravi | 2012-10-09 |
| 8205125 | Enhanced control in scan tests of integrated circuits with partitioned scan chains | Alan Hales, Srujan Kumar Nakidi, Srivaths Ravi, Rajesh Tiwari | 2012-06-19 |
| 7213184 | Testing of modules operating with different characteristics of control signals using scan based techniques | Nikila Krishnamoorthy, Anindya Saha | 2007-05-01 |
| 7203880 | Generating an abbreviated netlist including pseudopin inputs and output nodes | Srinivasa Chakravarthy, Julio Hernandez, Kenneth M. Butler | 2007-04-10 |
| 7134061 | At-speed ATPG testing and apparatus for SoC designs having multiple clock domain using a VLCT test platform | Anupama Aniruddha Agashe, Nikila Krishnamoorthy, Anindya Saha | 2006-11-07 |
| 7120842 | Mechanism to enhance observability of integrated circuit failures during burn-in tests | Gordhan Barevadia, Anupama Aniruddha Agashe, Nikila Krishnamoorthy, Neil John Simpson | 2006-10-10 |
| 6925408 | Mixed-signal core design for concurrent testing of mixed-signal, analog, and digital components | Amit Premy, Vudutha V. N. Suresh Gupta, Anupama Aniruddha Agashe, Nikila Krishnamoorthy | 2005-08-02 |
| 6697982 | Generating netlist test vectors by stripping references to a pseudo input | Srinivasa Chakravarthy, Julio Hernandez, Kenneth M. Butler | 2004-02-24 |