Issued Patents All Time
Showing 1–25 of 28 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12407557 | Power efficient crest factor reduction | Jaiganesh Balakrishnan, Aswath VS, Sriram Murali, Sreenath Narayanan Potty, Girish Nadiger +1 more | 2025-09-02 |
| 12160259 | Low power digital modes for duty-cycled integrated transceivers | Nagalinga Swamy Basayya Aremallapur, Kalyan Gudipati, Divyeshkumar Mahendrabhai PATEL, Venkateshwara Reddy Pothapu, Aravind Vijayakumar +2 more | 2024-12-03 |
| 11757475 | Low-complexity inverse sinc for RF sampling transmitters | Jaiganesh Balakrishnan, Sriram Murali, Yeswanth Guntupalli | 2023-09-12 |
| 11709203 | Transition fault testing of functionally asynchronous paths in an integrated circuit | Prakash Narayanan, Prashanth Saraf | 2023-07-25 |
| 11422586 | Methods and systems for generation of balanced secondary clocks from root clock | Aswath VS, Sarma Sundareswara Gunturi, Sanjay Pennam | 2022-08-23 |
| 11320488 | Self test for safety logic | Saket Jalan | 2022-05-03 |
| 11300615 | Transistion fault testing of funtionally asynchronous paths in an integrated circuit | Prakash Narayanan, Prashanth Saraf | 2022-04-12 |
| 11204385 | Transition fault test (TFT) clock receiver system | Gautam Sanjay Kale, Nagalinga Swamy Basayya Aremallapur | 2021-12-21 |
| 11171674 | Low-complexity inverse sinc for RF sampling transmitters | Jaiganesh Balakrishnan, Sriram Murali, Yeswanth Guntupalli | 2021-11-09 |
| 11095485 | Frequency-domain IQ mismatch estimation | Jawaharlal Tangudu, Sashidharan Venkatraman, Sarma Sundareswara Gunturi, Sthanunathan Ramakrishnan | 2021-08-17 |
| 10935602 | Self test for safety logic | Saket Jalan | 2021-03-02 |
| 10911057 | Digital clock generation with randomized division of a source clock | Sarma Sundareswara Gunturi, Jawaharlal Tangudu | 2021-02-02 |
| 10812091 | Dithered M by N clock dividers | Sriram Murali, Sanjay Pennam | 2020-10-20 |
| 10651863 | Dithered M by N clock dividers | Sriram Murali, Sanjay Pennam | 2020-05-12 |
| 10651836 | Clock pulse generator | Gautam Sanjay Kale, Nagalinga Swamy Basayya Aremallapur | 2020-05-12 |
| 10574246 | Digital downconverter with digital oscillator frequency error correction | Sarma Sundareswara Gunturi, Aswath VS, Raunak Dhaniwala | 2020-02-25 |
| 10396829 | Transformation based filter for interpolation or decimation | Jaiganesh Balakrishnan, Suvam Nandi | 2019-08-27 |
| 10320412 | Memory compression operable for non-contiguous write/read addresses | Desmond Pravin Martin Fernandes, Rakesh Channabasappa Yaraduyathinahalli | 2019-06-11 |
| 10305451 | Multiplier-based programmable filters | Jaiganesh Balakrishnan, Jawaharlal Tangudu, Srinivas Kumar Reddy Naru | 2019-05-28 |
| 10090866 | Transformation based filter for interpolation or decimation | Jaiganesh Balakrishnan, Suvam Nandi | 2018-10-02 |
| 9964597 | Self test for safety logic | Saket Jalan | 2018-05-08 |
| 9929744 | Memory compression operable for non-contiguous write/read addresses | Desmond Pravin Martin Fernandes, Rakesh Channabasappa Yaraduyathinahalli | 2018-03-27 |
| 9680677 | Weather band receiver | Sriram Murali, Indu Prathapan, Pankaj Gupta, Zahir Ibrahim Parkar | 2017-06-13 |
| 9531343 | Systems and methods of variable fractional rate digital resampling | Jawaharlal Tangudu, Sachin Bharadwaj | 2016-12-27 |
| 9491012 | Direct over-sampled pulse shaping circuit with flip flops and LUT | Jaiganesh Balakrishnan, Sriram Murali, Sarma Sundareswara Gunturi | 2016-11-08 |