Issued Patents All Time
Showing 1–18 of 18 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12160259 | Low power digital modes for duty-cycled integrated transceivers | Sundarrajan Rangachari, Kalyan Gudipati, Divyeshkumar Mahendrabhai PATEL, Venkateshwara Reddy Pothapu, Aravind Vijayakumar +2 more | 2024-12-03 |
| 11695602 | Filtered coarse mixer based digital down-converter for RF sampling ADCs | Jaiganesh Balakrishnan, Aswath VS | 2023-07-04 |
| 11569827 | Analog-to-digital convertor pseudo periodic IL estimation | Sthanunathan Ramakrishnan, Nithin Gopinath, Sai Aditya Nurani, Joseph Palackal Mathew | 2023-01-31 |
| 11469928 | Offset correction in high-speed serial link receivers | Ani Xavier, Jagannathan Venkataraman, Aviral Singhal, Arun Mohan, Rakesh Manjunath +2 more | 2022-10-11 |
| 11418148 | Phase coherent numerically controlled oscillator | Sriram Murali, Jawaharlal Tangudu | 2022-08-16 |
| 11204385 | Transition fault test (TFT) clock receiver system | Gautam Sanjay Kale, Sundarrajan Rangachari | 2021-12-21 |
| 10879845 | Phase coherent numerically controlled oscillator | Sriram Murali, Jawaharlal Tangudu | 2020-12-29 |
| 10840919 | Frequency domain-based clock recovery | Shyam Subramanian, Jagannathan Venkataraman, Aravind Ganesan | 2020-11-17 |
| 10693444 | Mixed signal circuit spur cancellation | Eeshan Miglani, Visvesvaraya Pentakota, Praxal Sunilkumar Shah | 2020-06-23 |
| 10651836 | Clock pulse generator | Gautam Sanjay Kale, Sundarrajan Rangachari | 2020-05-12 |
| 10341082 | Delay modulated clock division | Jaiganesh Balakrishnan, Shagun Dusad, Visvesvaraya Pentakota, Srinivas Kumar Reddy Naru, Sarma Sundareswara Gunturi | 2019-07-02 |
| 10205455 | Universal oscillator | — | 2019-02-12 |
| 9455720 | Universal oscillator | — | 2016-09-27 |
| 9344066 | Digital open loop duty cycle correction circuit | — | 2016-05-17 |
| 8786347 | Delay circuits for simulating delays based on a single cycle of a clock signal | Abhishek Chakraborty, Vikas Narang | 2014-07-22 |
| 8686777 | Methods and circuits for enabling slew rate programmability and compensation of input/output circuits | Vikas Narang, Abhishek Chakraborty | 2014-04-01 |
| 8542049 | Methods and delay circuits for generating a plurality of delays in delay lines | Keshav Chintamani Bhaktavatson | 2013-09-24 |
| 8253457 | Delay locked loop with delay programmability | — | 2012-08-28 |