Issued Patents All Time
Showing 25 most recent of 48 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12244288 | Balun with improved common mode rejection ratio | Vysakh Karthikeyan, Naveen Mahadev, Rafi Mahammad | 2025-03-04 |
| 12206427 | Lookup table for non-linear systems | Visvesvaraya Pentakota, Srinivas Kumar Reddy Naru, Chirag Chandrahas Shetty, Eeshan Miglani, Neeraj Shrivastava +1 more | 2025-01-21 |
| 12191877 | Multi-bit voltage-to-delay conversion in data converter circuitry | Sai Aditya Nurani, Rishi Soundararajan, Nithin Gopinath, Visvesvaraya Pentakota | 2025-01-07 |
| 11916567 | Current-based track and hold circuit | Sai Aditya Nurani, Joseph Palackal Mathew, Prasanth K, Visvesvaraya Pentakota | 2024-02-27 |
| 11888459 | Balun with improved common mode rejection ratio | Vysakh Karthikeyan, Naveen Mahadev, Rafi Mahammad | 2024-01-30 |
| 11881867 | Calibration scheme for filling lookup table in an ADC | Narasimhan Rajagopal, Eeshan Miglani, Chirag Chandrahas Shetty, Neeraj Shrivastava, Srinivas Kumar Reddy Naru +8 more | 2024-01-23 |
| 11831283 | Time gain compensation circuit in an ultrasound receiver | Vajeed Nimran, Raja Sekhar, Sandeep Kesrimal Oswal | 2023-11-28 |
| 11489515 | Clock filter with negative resistor circuit | Eeshan Miglani | 2022-11-01 |
| 11424758 | Conversion and folding circuit for delay-based analog-to-digital converter system | Chirag Chandrahas Shetty, Visvesvaraya Pentakota | 2022-08-23 |
| 11309902 | Gain and memory error estimation in a pipeline analog to digital converter | Srinivas Kumar Reddy Naru, Narasimhan Rajagopal, Viswanathan Nagarajan, Visvesvaraya Pentakota | 2022-04-19 |
| 11277145 | Current-based track and hold circuit | Sai Aditya Nurani, Joseph Palackal Mathew, Prasanth K, Visvesvaraya Pentakota | 2022-03-15 |
| 11239851 | Gain correction for multi-bit successive-approximation register | Srinivas Kumar Reddy Naru, Anand Jerry George, Visvesvaraya Pentakota | 2022-02-01 |
| 11139799 | Clock filter with negative resistor circuit | Eeshan Miglani | 2021-10-05 |
| 11031947 | Conversion and folding circuit for delay-based analog-to-digital converter system | Chirag Chandrahas Shetty, Visvesvaraya Pentakota | 2021-06-08 |
| 10985769 | Transceiver with in-phase and quadrature-phase coupling correction | Raja Reddy Patukuri, Jagannathan Venkataraman | 2021-04-20 |
| 10985708 | Time gain compensation circuit in an ultrasound receiver | Vajeed Nimran, Raja Sekhar, Sandeep Kesrimal Oswal | 2021-04-20 |
| 10903845 | Delay-based residue stage | Visvesvaraya Pentakota, Rishi Soundararajan, Chirag Chandrahas Shetty | 2021-01-26 |
| 10892835 | Bias removal in PRBS based channel estimation | Nagarajan Viswanathan | 2021-01-12 |
| 10790841 | Gain correction for multi-bit successive-approximation register | Srinivas Kumar Reddy Naru, Anand Jerry George, Visvesvaraya Pentakota | 2020-09-29 |
| 10778243 | Delay-based residue stage | Visvesvaraya Pentakota, Rishi Soundararajan, Chirag Chandrahas Shetty | 2020-09-15 |
| 10686461 | Top plate sampling analog-to-digital converter (ADC) with residue amplifier non-linearity reduction | Sai Aditya Nurani, Arun Mohan, Neeraj Shrivastava | 2020-06-16 |
| 10673456 | Conversion and folding circuit for delay-based analog-to-digital converter system | Chirag Chandrahas Shetty, Visvesvaraya Pentakota | 2020-06-02 |
| 10673453 | Delay-based residue stage | Visvesvaraya Pentakota, Rishi Soundararajan, Chirag Chandrahas Shetty | 2020-06-02 |
| 10637491 | Transceiver with in-phase and quadrature-phase coupling correction | Raja Reddy Patukuri, Jagannathan Venkataraman | 2020-04-28 |
| 10541700 | Gain and memory error estimation in a pipeline analog to digital converter | Srinivas Kumar Reddy Naru, Narasimhan Rajagopal, Viswanathan Nagarajan, Visvesvaraya Pentakota | 2020-01-21 |