Issued Patents All Time
Showing 1–11 of 11 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12334946 | Asynchronous analog-to-digital converter | Rajashekar Goroju, Dileepkumar Ramesh Bhat, Rahul Sharma | 2025-06-17 |
| 12261620 | Methods and apparatus to capture switch charge injections and comparator kickback effects | Rajashekar Goroju, Dileepkumar Ramesh Bhat, Rakul Viswanath, Sravana Kumar Goli, Rahul Sharma | 2025-03-25 |
| 12206424 | Methods and apparatus to reduce inter-stage gain errors in analog-to-digital converters | Rahul Sharma | 2025-01-21 |
| 12101096 | Differential voltage-to-delay converter with improved CMRR | Eeshan Miglani, Visvesvaraya Pentakota, Kartik Goel, Jagannathan Venkataraman, Sai Aditya Nurani | 2024-09-24 |
| 11916567 | Current-based track and hold circuit | Sai Aditya Nurani, Joseph Palackal Mathew, Visvesvaraya Pentakota, Shagun Dusad | 2024-02-27 |
| 11881867 | Calibration scheme for filling lookup table in an ADC | Narasimhan Rajagopal, Eeshan Miglani, Chirag Chandrahas Shetty, Neeraj Shrivastava, Shagun Dusad +8 more | 2024-01-23 |
| 11689210 | Methods and apparatus to calibrate a dual-residue pipeline analog to digital converter | Srinivas Kumar Reddy Naru, Visvesvaraya Pentakota | 2023-06-27 |
| 11438001 | Gain mismatch correction for voltage-to-delay preamplifier array | Narasimhan Rajagopal, Chirag Chandrahas Shetty, Neeraj Shrivastava, Eeshan Miglani | 2022-09-06 |
| 11316525 | Lookup-table-based analog-to-digital converter | Visvesvaraya Pentakota, Narasimhan Rajagopal, Chirag Chandrahas Shetty, Neeraj Shrivastava, Eeshan Miglani +1 more | 2022-04-26 |
| 11277145 | Current-based track and hold circuit | Sai Aditya Nurani, Joseph Palackal Mathew, Visvesvaraya Pentakota, Shagun Dusad | 2022-03-15 |
| 10637521 | 25% duty cycle clock generator having a divider with an inverter ring arrangement | — | 2020-04-28 |