Issued Patents All Time
Showing 1–13 of 13 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12388688 | Pretap equalizable continuous time linear equalizer | Jagannathan Venkataraman, Arun Mohan | 2025-08-12 |
| 11956340 | Methods and apparatus to reduce retimer latency and jitter | Jagannathan Venkataraman | 2024-04-09 |
| 11855816 | Signal transmission system for use with eye diagram monitor | Rakesh Manjunath, Aravind Ganesan, Jagannathan Venkataraman, Abhishek Agrawal, Charls Babu +1 more | 2023-12-26 |
| 11722142 | Charge pump with output current adjustment | Jagannathan Venkataraman, Shyam Subramanian | 2023-08-08 |
| 11469928 | Offset correction in high-speed serial link receivers | Jagannathan Venkataraman, Nagalinga Swamy Basayya Aremallapur, Aviral Singhal, Arun Mohan, Rakesh Manjunath +2 more | 2022-10-11 |
| 11416021 | Calibration of skew between clock phases | Jagannathan Venkataraman, Raviteja Velisetti | 2022-08-16 |
| 11063793 | Serial receiver equalization circuit | Jagannathan Venkataraman, Sandeep Kesrimal Oswal | 2021-07-13 |
| 10439628 | Top plate sampling circuit including input-dependent dual clock boost circuits | Neeraj Shrivastava, Arun Mohan | 2019-10-08 |
| 10425042 | Negative capacitance circuits including temperature-compensation biasings | Neeraj Shrivastava, Arun Mohan, Shagun Dusad | 2019-09-24 |
| 10396766 | Parasitic capacitance cancellation using dummy transistors | Basavaraj G. Gorguddi | 2019-08-27 |
| 10320405 | Pattern based estimation of errors in ADC | Srinivas Kumar Reddy Naru, Visvesvaraya Pentakota Appala, Shagun Dusad, Neeraj Shrivastava, Viswanathan Nagarajan +3 more | 2019-06-11 |
| 10084466 | Top plate sampling circuit including input-dependent dual clock boost circuits | Neeraj Shrivastava, Arun Mohan | 2018-09-25 |
| 9941893 | Pattern based estimation of errors in ADC | Srinivas Kumar Reddy Naru, Visvesvaraya Pentakota Appala, Shagun Dusad, Neeraj Shrivastava, Viswanathan Nagarajan +3 more | 2018-04-10 |