Issued Patents All Time
Showing 26–50 of 147 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11121040 | Multi voltage threshold transistors through process and design-induced multiple work functions | Chen-Guan Lee, Everett S. Cassidy-Comfort, Joodong Park, Walid M. Hafez, Rahul Ramaswamy +2 more | 2021-09-14 |
| 11114538 | Transistor with an airgap spacer adjacent to a transistor gate | Chen-Guan Lee, Joodong Park, En-Shao Liu, Everett S. Cassidy-Comfort, Walid M. Hafez | 2021-09-07 |
| 11075286 | Hybrid finfet structure with bulk source/drain regions | Walid M. Hafez, Neville L. Dias, Rahul Ramaswamy, Hsu-Yu Chang, Roman W. Olac-Vaw +1 more | 2021-07-27 |
| 10964690 | Resistor between gates in self-aligned gate edge architecture | Roman W. Olac-Vaw, Walid M. Hafez, Hsu-Yu Chang, Neville L. Dias, Rahul Ramaswamy +2 more | 2021-03-30 |
| 10950606 | Dual fin endcap for self-aligned gate edge (SAGE) architectures | Walid M. Hafez, Roman W. Olac-Vaw | 2021-03-16 |
| 10930729 | Fin-based thin film resistor | Walid M. Hafez, Neville L. Dias, Rahul Ramaswamy, Hsu-Yu Chang, Roman W. Olac-Vaw +1 more | 2021-02-23 |
| 10923574 | Transistor with inner-gate spacer | En-Shao Liu, Joodong Park, Chen-Guan Lee, Jui-Yen Lin | 2021-02-16 |
| 10903372 | Metal-oxide-polysilicon tunable resistor for flexible circuit design and method of fabricating same | Kinyip Phoa, Jui-Yen Lin, Nidhi Nidhi | 2021-01-26 |
| 10892261 | Metal resistor and self-aligned gate edge (SAGE) architecture having a metal resistor | Walid M. Hafez, Roman W. Olac-Vaw, Joodong Park, Chen-Guan Lee | 2021-01-12 |
| 10892192 | Non-planar I/O and logic semiconductor devices having different workfunction on common substrate | Roman W. Olac-Vaw, Walid M. Hafez, Pei-Chi Liu | 2021-01-12 |
| 10854607 | Isolation well doping with solid-state diffusion sources for finFET architectures | Walid M. Hafez, Jeng-Ya David Yeh, Hsu-Yu Chang, Neville L. Dias, Chanaka D. Munasinghe | 2020-12-01 |
| 10854757 | FINFET based junctionless wrap around structure | Rahul Ramaswamy, Hsu-Yu Chang, Walid M. Hafez, Neville L. Dias, Roman W. Olac-Vaw +1 more | 2020-12-01 |
| 10847544 | High voltage three-dimensional devices having dielectric liners | Walid M. Hafez, Jeng-Ya David Yeh, Curtis Tsai, Joodong Park, Gopinath Bhimarasetti | 2020-11-24 |
| 10847456 | Antifuse element using spacer breakdown | Ting Chang, Walid M. Hafez | 2020-11-24 |
| 10811751 | Monolithic splitter using re-entrant poly silicon waveguides | Rahul Ramaswamy, Walid M. Hafez, Neville L. Dias, Hsu-Yu Chang, Roman W. Olac-Vaw +1 more | 2020-10-20 |
| 10784378 | Ultra-scaled fin pitch having dual gate dielectrics | Walid M. Hafez, Roman W. Olac-Vaw, Joodong Park, Chen-Guan Lee, Everett S. Cassidy-Comfort | 2020-09-22 |
| 10763209 | MOS antifuse with void-accelerated breakdown | Roman W. Olac-Vaw, Walid M. Hafez, Hsu-Yu Chang, Ting Chang, Rahul Ramaswamy +2 more | 2020-09-01 |
| 10761264 | Transmission lines using bending fins from local stress | Rahul Ramaswamy, Walid M. Hafez, Neville L. Dias, Hsu-Yu Chang, Roman W. Olac-Vaw +1 more | 2020-09-01 |
| 10756210 | Depletion mode gate in ultrathin FINFET based architecture | Walid M. Hafez, Hsu-Yu Chang, Neville L. Dias, Rahul Ramaswamy, Roman W. Olac-Vaw +1 more | 2020-08-25 |
| 10741640 | Dielectric and isolation lower Fin material for Fin-based electronics | Walid M. Hafez | 2020-08-11 |
| 10707346 | High-voltage transistor with self-aligned isolation | Walid M. Hafez | 2020-07-07 |
| 10692888 | High voltage three-dimensional devices having dielectric liners | Walid M. Hafez, Jeng-Ya David Yeh, Curtis Tsai, Joodong Park, Gopinath Bhimarasetti | 2020-06-23 |
| 10692771 | Non-planar I/O and logic semiconductor devices having different workfunction on common substrate | Roman W. Olac-Vaw, Walid M. Hafez, Pei-Chi Liu | 2020-06-23 |
| 10658361 | Methods of integrating multiple gate dielectric transistors on a tri-gate (FINFET) process | Curtis Tsai, Jeng-Ya David Yeh, Joodong Park, Walid M. Hafez | 2020-05-19 |
| 10643999 | Doping with solid-state diffusion sources for finFET architectures | Walid M. Hafez, Jeng-Ya David Yeh, Hsu-Yu Chang, Neville L. Dias, Chanaka D. Munasinghe | 2020-05-05 |