| 11804470 |
Wafer level passive heat spreader interposer to enable improved thermal solution for stacked dies in multi-chips package and warpage control |
Xavier Francois Brun, Paul R. Start, Nisha Ananthakrishnan, Yawei Liang, Jigneshkumar P. Patel +2 more |
2023-10-31 |
$30,374,000 |
| 9735270 |
Semiconductor transistor having a stressed channel |
Anand S. Murthy, Robert S. Chau, Tahir Ghani |
2017-08-15 |
$8,272,000 |
| 9490364 |
Semiconductor transistor having a stressed channel |
Anand S. Murthy, Robert S. Chau, Tahir Ghani |
2016-11-08 |
$9,907,000 |
| 8766372 |
Copper-filled trench contact for transistor performance improvement |
Kelin J. Kuhn, Mark Bohr, Chris Auth |
2014-07-01 |
$13,029,000 |
| 8258057 |
Copper-filled trench contact for transistor performance improvement |
Kelin J. Kuhn, Mark Bohr, Chris Auth |
2012-09-04 |
$13,616,000 |
| 6979609 |
Method of fabricating MOSFET transistors with multiple threshold voltages by halo compensation and masks |
Ian R. Post |
2005-12-27 |
$17,238,000 |
| 6956263 |
Field effect transistor structure with self-aligned raised source/drain extensions |
— |
2005-10-18 |
$19,273,000 |
| 6903598 |
Static, low-voltage fuse-based cell with high-voltage programming |
Martin S. Denham, Mohsen Alavi, Patrick J. Ott, Rachael Parker, Paul Gregory Slankard +1 more |
2005-06-07 |
$27,808,000 |
| 6885084 |
Semiconductor transistor having a stressed channel |
Anand S. Murthy, Robert S. Chau, Tahir Ghani |
2005-04-26 |
$30,166,000 |
| 6861318 |
Semiconductor transistor having a stressed channel |
Anand S. Murthy, Robert S. Chau, Tahir Ghani |
2005-03-01 |
$28,008,000 |
| 6803285 |
Method of fabricating dual threshold voltage n-channel and p-channel mosfets with a single extra masked implant operation |
Ian R. Post |
2004-10-12 |
$44,708,000 |
| 6717221 |
Method of fabricating MOSFET transistors with multiple threshold voltages by halo compensation and masks |
Ian R. Post |
2004-04-06 |
$23,009,000 |
| 6716046 |
Field effect transistor structure with self-aligned raised source/drain extensions |
— |
2004-04-06 |
$23,009,000 |
| 6693331 |
Method of fabricating dual threshold voltage n-channel and p-channel MOSFETS with a single extra masked implant operation |
Ian R. Post |
2004-02-17 |
$33,660,000 |
| 6621131 |
Semiconductor transistor having a stressed channel |
Anand S. Murthy, Robert S. Chau, Tahir Ghani |
2003-09-16 |
$36,866,000 |
| 6586294 |
Method of fabricating MOSFET transistors with multiple threshold voltages by halo compensation and masks |
Ian R. Post |
2003-07-01 |
$52,453,000 |
| 6362034 |
Method of forming MOSFET gate electrodes having reduced depletion region growth sensitivity to applied electric field |
Justin S. Sandford |
2002-03-26 |
$63,938,000 |
| 6352913 |
Damascene process for MOSFET fabrication |
Lawrence Bair |
2002-03-05 |
$51,196,000 |
| 6078487 |
Electro-static discharge protection device having a modulated control input terminal |
Hamid Partovi, David Benjamin Krakauer, William McGee |
2000-06-20 |
|
| 5930605 |
Compact self-aligned body contact silicon-on-insulator transistors |
Jeffrey W. Sleight |
1999-07-27 |
|
| 5821575 |
Compact self-aligned body contact silicon-on-insulator transistor |
Jeffrey W. Sleight |
1998-10-13 |
|
| 5617283 |
Self-referencing modulation circuit for CMOS integrated circuit electrostatic discharge protection clamps |
David Benjamin Krakauer, Steven Butler, Hamid Partovi |
1997-04-01 |
$22,455,000 |
| 5525829 |
Field effect transistor with integrated schottky diode clamp |
— |
1996-06-11 |
$26,646,000 |
| 5262344 |
N-channel clamp for ESD protection in self-aligned silicided CMOS process |
— |
1993-11-16 |
$7,719,000 |
| 5021853 |
N-channel clamp for ESD protection in self-aligned silicided CMOS process |
— |
1991-06-04 |
$22,428,000 |
