Issued Patents All Time
Showing 25 most recent of 26 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11756977 | Backside illumination image sensors | Jeffrey P. Gambino, David T. Price | 2023-09-12 |
| 9711556 | Semiconductor image sensor structure having metal-filled trench contact | David T. Price, Sungkwon Hong, Gordon M. Grivna | 2017-07-18 |
| 9570494 | Method for forming a semiconductor image sensor device | David T. Price, Sungkwon Hong, Gordon M. Grivna | 2017-02-14 |
| 9257525 | Systems and methods for forming isolated devices in a handle wafer | I-Shan Sun, Francois Hebert | 2016-02-09 |
| 8815641 | Diamond SOI with thin silicon nitride layer and related methods | Francois Hebert, Craig J. McLachlan, Kevin Hoopingarner | 2014-08-26 |
| 8691670 | Methods of forming a semiconductor device | Francois Hebert, Craig J. McLachlan, Kevin Hoopingarner | 2014-04-08 |
| 8476150 | Methods of forming a semiconductor device | Francois Hebert, Craig J. McLachlan, Kevin Hoopingarner | 2013-07-02 |
| 6069078 | Multi-level interconnect metallization technique | James C. Weaver | 2000-05-30 |
| 5670394 | Method of making bipolar transistor having amorphous silicon contact as emitter diffusion source | Ian R. Post | 1997-09-23 |
| 5661046 | Method of fabricating BiCMOS device | Vida Ilderem, Ali A. Iranmanesh, Alan Glen Solheim, Christopher S. Blair, Rajeeva Lahri +1 more | 1997-08-26 |
| 5565370 | Method of enhancing the current gain of bipolar junction transistors | Ian R. Post, Gary M. Wodek | 1996-10-15 |
| 5561073 | Method of fabricating an isolation trench for analog bipolar devices in harsh environments | Ian R. Post | 1996-10-01 |
| 5525533 | Method of making a low voltage coefficient capacitor | Richard L. Woodruff | 1996-06-11 |
| 5493149 | Transistor device with increased breakdown voltage | Brian R. McFarlane, Frank Marazita | 1996-02-20 |
| 5436496 | Vertical fuse device | Ronald P. Kovacs, George E. Ganschow, Lawrence K. Lam, James L. Bouknight, Frank Marazita +2 more | 1995-07-25 |
| 5420050 | Method of enhancing the current gain of bipolar junction transistors | Ian R. Post, Gary M. Wodek | 1995-05-30 |
| 5350942 | Low resistance silicided substrate contact | Frank Marazita | 1994-09-27 |
| 5344785 | Method of forming high speed, high voltage fully isolated bipolar transistors on a SOI substrate | Diane R. Williams, Kurt D. Humphrey | 1994-09-06 |
| 5338696 | Method of fabricating BiCMOS device | Vida Ilderem, Ali A. Iranmanesh, Alan Glen Solheim, Christopher S. Blair, Rajeeva Lahri +1 more | 1994-08-16 |
| 5338694 | Method of fabricating BiCMOS device | Vida Ilderem, Ali A. Iranmanesh, Alan Glen Solheim, Christopher S. Blair, Rajeeva Lahri +1 more | 1994-08-16 |
| 5298440 | Method of fabrication of transistor device with increased breakdown voltage | Brian R. McFarlane, Frank Marazita | 1994-03-29 |
| 5231042 | Formation of silicide contacts using a sidewall oxide process | Vida Ilderem, Alan Glen Solheim | 1993-07-27 |
| 5139961 | Reducing base resistance of a BJT by forming a self aligned silicide in the single crystal region of the extrinsic base | Alan Glen Solheim, Bamdad Bastani, James L. Bouknight, George E. Ganschow, Bancherd DeLong +7 more | 1992-08-18 |
| 5139966 | Low resistance silicided substrate contact | Frank Marazita | 1992-08-18 |
| 5107321 | Interconnect method for semiconductor devices | Vida Ilderem, Alan Glen Solheim | 1992-04-21 |