Issued Patents All Time
Showing 25 most recent of 31 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12374584 | Multi color stack for self aligned dual pattern formation for multi purpose device structures | Suketu Arun Parikh, Martin Jay Seamons, Jingmei Liang, Shuchi Sunil Ojha, Tom Choi +1 more | 2025-07-29 |
| 12062708 | Selective silicon etch for gate all around transistors | Michael Stolfi, Myungsun Kim, Benjamin Colombeau | 2024-08-13 |
| 11749315 | 3D DRAM structure with high mobility channel | Chang-Seok Kang, Tomohiko Kitajima, Gill Yong Lee, Sung-Kwan Kang, Lequn Liu | 2023-09-05 |
| 11705335 | Conformal high concentration boron doping of semiconductors | Srinivas Gandikota, Abhijit Basu Mallick, Swaminathan Srinivasan, Rui Cheng, Susmit Singha Roy +2 more | 2023-07-18 |
| 11682668 | Stacked transistor device | Suketu Arun Parikh | 2023-06-20 |
| 11621266 | Method of testing a gap fill for DRAM | Priyadarshi Panda, Seshadri Ganguli, Sang Ho Yu, Sung-Kwan Kang, Gill Yong Lee +2 more | 2023-04-04 |
| 11508828 | Selective silicon etch for gate all around transistors | Michael Stolfi, Myungsun Kim, Benjamin Colombeau | 2022-11-22 |
| 11462411 | Gate contact over active regions | Gaurav Thareja, Keyvan Kashefizadeh, Xikun Wang, Anchuan Wang, Sean M. Seutter +1 more | 2022-10-04 |
| 11437273 | Self-aligned contact and contact over active gate structures | Yuriy Shusterman, Madhur Sachan, Susmit Singha Roy, Regina Freed | 2022-09-06 |
| 11328928 | Conformal high concentration boron doping of semiconductors | Srinivas Gandikota, Abhijit Basu Mallick, Swaminathan Srinivasan, Rui Cheng, Susmit Singha Roy +2 more | 2022-05-10 |
| 11309404 | Integrated CMOS source drain formation with advanced control | Benjamin Colombeau, Tushar Mandrekar, Patricia M. Liu, Suketu Arun Parikh, Matthias Bauer +2 more | 2022-04-19 |
| 11295786 | 3D dram structure with high mobility channel | Chang-Seok Kang, Tomohiko Kitajima, Gill Yong Lee, Sung-Kwan Kang, Lequn Liu | 2022-04-05 |
| 11195923 | Method of fabricating a semiconductor device having reduced contact resistance | Gaurav Thareja, Xuebin Li, Abhishek Dube, Yi-Chiau Huang, Tushar Mandrekar +3 more | 2021-12-07 |
| 11189635 | 3D-NAND mold | Chang-Seok Kang, Tomohiko Kitajima, Mukund Srinivasan | 2021-11-30 |
| 11177254 | Stacked transistor device | Suketu Arun Parikh | 2021-11-16 |
| 11171141 | Gap fill methods of forming buried word lines in DRAM without forming bottom voids | Priyadarshi Panda, Seshadri Ganguli, Sang Ho Yu, Sung-Kwan Kang, Gill Yong Lee +2 more | 2021-11-09 |
| 11164938 | DRAM capacitor module | Uday Mitra, Regina Freed, Ho-yung David Hwang, Lequn Liu | 2021-11-02 |
| 11152479 | Semiconductor device, method of making a semiconductor device, and processing system | Gaurav Thareja, Xuebin Li, Abhishek Dube, Yi-Chiau Huang, Andy Lo +2 more | 2021-10-19 |
| 11114320 | Processing system and method of forming a contact | Gaurav Thareja, Takashi Kuratomi, Avgerinos V. Gelatos, Xianmin Tang, Keyvan Kashefizadeh +3 more | 2021-09-07 |
| 11004687 | Gate contact over active processes | Gaurav Thareja, Keyvan Kashefizadeh, Xikun Wang, Anchuan Wang, Sean M. Seutter +1 more | 2021-05-11 |
| 10903112 | Methods and apparatus for smoothing dynamic random access memory bit line metal | Priyadarshi Panda, Jianxin Lei, In-Seok Hwang, Nobuyuki Sasaki | 2021-01-26 |
| 10892187 | Method for creating a fully self-aligned via | Regina Freed, Uday Mitra | 2021-01-12 |
| 10700072 | Cap layer for bit line resistance reduction | Priyadarshi Panda, Jianxin Lei, Wenting Hou, Mihaela Balseanu, Ning Li +4 more | 2020-06-30 |
| 10553485 | Methods of producing fully self-aligned vias and contacts | Ying Zhang, Regina Freed, Nitin K. Ingle, Ho-yung David Hwang, Uday Mitra +1 more | 2020-02-04 |
| 10529602 | Method and apparatus for substrate fabrication | Priyadarshi Panda, Gill Yong Lee, Srinivas Gandikota, Sung-Kwan Kang | 2020-01-07 |