JP

Jayanthi Pallinti

Lsi Logic: 16 patents #84 of 1,957Top 5%
LS Lsi: 3 patents #448 of 1,740Top 30%
Overall (All Time): #240,673 of 4,157,543Top 6%
19
Patents All Time

Issued Patents All Time

Patent #TitleCo-InventorsDate
8552560 Alternate pad structures/passivation inegration schemes to reduce or eliminate IMC cracking in post wire bonded dies during Cu/Low-K BEOL processing Hemanshu Bhatt, Dilip Vijay, Sey-Shing Sun, Hong Ying, Chiyi Kao 2013-10-08
8076779 Reduction of macro level stresses in copper/low-K wafers Sey-Shing Sun, Dilip Vijay, Hemanshu Bhatt, Hong Ying, Chiyi Kao +1 more 2011-12-13
7531442 Eliminate IMC cracking in post wirebonded dies: macro level stress reduction by modifying dielectric/metal film stack in be layers during Cu/Low-K processing Dilip Vijay, Hemanshu Bhatt, Sey-Shing Sun, Hong Ying, Chiyi Kao +3 more 2009-05-12
7205673 Reduce or eliminate IMC cracking in post wire bonded dies by doping aluminum used in bond pads during Cu/Low-k BEOL processing Dilip Vijay, Hemanshu Bhatt, Sey-Shing Sun, Hong Ying, Chiyi Kao 2007-04-17
6951808 Metal planarization system Samuel V. Dunton, Ronald J. Nagahara 2005-10-04
6838379 PROCESS FOR REDUCING IMPURITY LEVELS, STRESS, AND RESISTIVITY, AND INCREASING GRAIN SIZE OF COPPER FILLER IN TRENCHES AND VIAS OF INTEGRATED CIRCUIT STRUCTURES TO ENHANCE ELECTRICAL PERFORMANCE OF COPPER FILLER Byung Sung Kwak, William K. Barth 2005-01-04
6752916 Electrochemical planarization end point detection Yan Fang, Ronald J. Nagahara 2004-06-22
6713394 Process for planarization of integrated circuit structure which inhibits cracking of low dielectric constant dielectric material adjacent underlying raised structures Ronald J. Nagahara, Dawn M. Lee 2004-03-30
6607967 Process for forming planarized isolation trench in integrated circuit structure on semiconductor substrate Dawn M. Lee, Ronald J. Nagahara 2003-08-19
6586326 Metal planarization system Samuel V. Dunton, Ronald J. Nagahara 2003-07-01
6555475 Arrangement and method for polishing a surface of a semiconductor wafer Ron Nagahara 2003-04-29
6503828 Process for selective polishing of metal-filled trenches of integrated circuit structures Ronald J. Nagahara, James J. Xie, Akihisa Ueno 2003-01-07
6489242 Process for planarization of integrated circuit structure which inhibits cracking of low dielectric constant dielectric material adjacent underlying raised structures Ronald J. Nagahara, Dawn M. Lee 2002-12-03
6439981 Arrangement and method for polishing a surface of a semiconductor wafer Ron Nagahara 2002-08-27
6424019 Shallow trench isolation chemical-mechanical polishing process Shouli Steve Hsia, Yanhua Wang 2002-07-23
6417093 Process for planarization of metal-filled trenches of integrated circuit structures by forming a layer of planarizable material over the metal layer prior to planarizing James J. Xie, Ronald J. Nagahara, Akihisa Ueno 2002-07-09
6391768 Process for CMP removal of excess trench or via filler metal which inhibits formation of concave regions on oxide surface of integrated circuit structure Dawn M. Lee, Weidan Li, Ming-Yi Lee 2002-05-21
6372524 Method for CMP endpoint detection James J. Xie, Ronald J. Nagahara 2002-04-16
6060370 Method for shallow trench isolations with chemical-mechanical polishing Shouli Steve Hsia, Yanhua Wang 2000-05-09