| 9734572 |
System and method for defect analysis of a substrate |
Yao-Wei Tien, Chi-Hung Liao |
2017-08-15 |
| 9449656 |
Memory with bit cell header transistor |
I-Han Huang, Chia-En Huang, Fu-An Wu, Jung-Ping Yang, Cheng Hung Lee |
2016-09-20 |
| 9412742 |
Layout design for manufacturing a memory cell |
Hidehiro Fujiwara, Kao-Cheng Lin, Yen-Huei Chen, Hung-Jen Liao |
2016-08-09 |
| 8965102 |
System and method for defect analysis of a substrate |
Yan-Wei Tien, Chi-Hung Liao |
2015-02-24 |
| 8665654 |
Memory edge cell |
Hong-Chen Cheng, Kuo-Hua Pan, Jung-Hsuan Chen, Li-Chun Tien, Cheng Hung Lee +1 more |
2014-03-04 |
| 8482990 |
Memory edge cell |
Hong-Chen Cheng, Kuo-Hua Pan, Jung-Hsuan Chen, Li-Chun Tien, Cheng Hung Lee +1 more |
2013-07-09 |
| 8226128 |
Releasable nut-free C-clip secured pipe fitting |
— |
2012-07-24 |
| 8021955 |
Method characterizing materials for a trench isolation structure having low trench parasitic capacitance |
Venkatesh P. Gopinath, Arvind Kamath, Mohammad Mirabedini |
2011-09-20 |
| 7619294 |
Shallow trench isolation structure with low trench parasitic capacitance |
Venkatesh P. Gopinath, Arvind Kamath, Mohammad Mirabedini |
2009-11-17 |
| 7001823 |
Method of manufacturing a shallow trench isolation structure with low trench parasitic capacitance |
Venkatesh P. Gopinath, Arvind Kamath, Mohammad Mirabedini |
2006-02-21 |
| 6989331 |
Hard mask removal |
Venkatesh P. Gopinath, Arvind Kamath, Mohammad Mirabedini, Brian A. Baylis |
2006-01-24 |
| 6916700 |
Mixed-mode process |
Yao Huang, Hui Chen |
2005-07-12 |
| 6737342 |
Composite spacer scheme with low overlapped parasitic capacitance |
Chien-Hwa Chang |
2004-05-18 |
| 6727165 |
Fabrication of metal contacts for deep-submicron technologies |
Helmut Puchner |
2004-04-27 |
| 6613637 |
Composite spacer scheme with low overlapped parasitic capacitance |
Chien-Hwa Chang |
2003-09-02 |
| 6604257 |
Apparatus and method for cleaning a conduit |
Ying Chen |
2003-08-12 |
| 6586332 |
Deep submicron silicide blocking |
— |
2003-07-01 |
| 6391768 |
Process for CMP removal of excess trench or via filler metal which inhibits formation of concave regions on oxide surface of integrated circuit structure |
Dawn M. Lee, Jayanthi Pallinti, Weidan Li |
2002-05-21 |
| 6319836 |
Planarization system |
Samuel V. Dunton |
2001-11-20 |
| 6315649 |
Wafer mounting plate for a polishing apparatus and method of using |
Tien-Chen Hu, Tsen-Hsing Yi, Chien-Hsien Lee |
2001-11-13 |
| 6127286 |
Apparatus and process for deposition of thin film on semiconductor substrate while inhibiting particle formation and deposition |
Kaijun Zhang, Wilbur C. Catabay |
2000-10-03 |
| 5851890 |
Process for forming integrated circuit structure with metal silicide contacts using notched sidewall spacer on gate electrode |
Jiunn-Yann Tsai, John Haywood |
1998-12-22 |
