Issued Patents All Time
Showing 1–9 of 9 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6495408 | Local interconnection process for preventing dopant cross diffusion in shared gate electrodes | Shouli Steve Hsia | 2002-12-17 |
| 6147409 | Modified multilayered metal line structure for use with tungsten-filled vias in integrated circuit structures | Shouli Steve Hsia, Fred Chen | 2000-11-14 |
| 6037262 | Process for forming vias, and trenches for metal lines, in multiple dielectric layers of integrated circuit structure | Shouli Steve Hsia | 2000-03-14 |
| 6034401 | Local interconnection process for preventing dopant cross diffusion in shared gate electrodes | Shouli Steve Hsia | 2000-03-07 |
| 6020242 | Effective silicide blocking | Shiuh-Luen Wang, Wen-Chin Yeh | 2000-02-01 |
| 6010952 | Process for forming metal silicide contacts using amorphization of exposed silicon while minimizing device degradation | Zhihai Wang, Wen-Chin Yeh | 2000-01-04 |
| 5874342 | Process for forming MOS device in integrated circuit structure using cobalt silicide contacts as implantation media | Zhihai Wang, Yen-Hui Ku | 1999-02-23 |
| 5851890 | Process for forming integrated circuit structure with metal silicide contacts using notched sidewall spacer on gate electrode | John Haywood, Ming-Yi Lee | 1998-12-22 |
| 5024954 | Method of improving high temperature stability of PTSI/SI structure | Mao-Chieh Chen, Bing-Yue Tsui | 1991-06-18 |