| 9449709 |
Volatile memory and one-time program (OTP) compatible memory cell and programming method |
Xia Li, Xiaonan Chen, Niladri Narayan Mojumder, Zhongze Wang |
2016-09-20 |
| 8946890 |
Power/ground layout for chips |
Sehat Sutardja, Chung Chyung Han, Shuhua Yu, Chuan-Cheng Cheng, Albert Wu |
2015-02-03 |
| 8921938 |
Laterally diffused metal oxide semiconductor (LDMOS) device with overlapping wells |
Xin Zhang, Chuan-Cheng Cheng, Jian-Hung Lee, Chung Chyung Han |
2014-12-30 |
| 7321254 |
On-chip automatic process variation, supply voltage variation, and temperature deviation (PVT) compensation method |
Benjamin Mbouombouo, Johann Leyrer |
2008-01-22 |
| 7181712 |
Method of optimizing critical path delay in an integrated circuit design |
Benjamin Mbouombouo, Dana Ahrens |
2007-02-20 |
| 7000163 |
Optimized buffering for JTAG boundary scan nets |
Juergen Dirks, Juergen Lahner, Ludger F. Johanterwage, Benjamin Mbouombouo, Human Boluki |
2006-02-14 |
| 6893962 |
Low via resistance system |
Prabhakar P. Tripathi, Zhihai Wang |
2005-05-17 |
| 6807656 |
Decoupling capacitance estimation and insertion flow for ASIC designs |
Lihui Cao, Prasad Subbarao, David Gradin, Maad Al-Dabagh |
2004-10-19 |
| 6794756 |
Integrated circuit structure having low dielectric constant material and having silicon oxynitride caps over closely spaced apart metal lines |
Wilbur G. Catabay, Wei-Jen Hsia |
2004-09-21 |
| 6756674 |
Low dielectric constant silicon oxide-based dielectric layer for integrated circuit structures having improved compatibility with via filler materials, and method of making same |
Wilbur G. Catabay, Wei-Jen Hsia, Joe W. Zhao |
2004-06-29 |
| 6608365 |
Low leakage PMOS on-chip decoupling capacitor cells compatible with standard CMOS cells |
Benjamin Mbouombouo, Johann Leyrer |
2003-08-19 |
| 6569751 |
Low via resistance system |
Prabhakar P. Tripathi, Zhihai Wang |
2003-05-27 |
| 6423628 |
Method of forming integrated circuit structure having low dielectric constant material and having silicon oxynitride caps over closely spaced apart metal lines |
Wilbur G. Catabay, Wei-Jen Hsia |
2002-07-23 |
| 6391768 |
Process for CMP removal of excess trench or via filler metal which inhibits formation of concave regions on oxide surface of integrated circuit structure |
Dawn M. Lee, Jayanthi Pallinti, Ming-Yi Lee |
2002-05-21 |
| 6329720 |
Tungsten local interconnect for silicon integrated circuit structures, and method of making same |
Wen-Chin Yeh, Rajat Rakkhit |
2001-12-11 |
