CH

Chung Chyung Han

IT Integrated Device Technology: 8 patents #65 of 758Top 9%
Disney: 6 patents #1,174 of 6,686Top 20%
Overall (All Time): #350,302 of 4,157,543Top 9%
14
Patents All Time

Issued Patents All Time

Patent #TitleCo-InventorsDate
9768144 Package assembly including a semiconductor substrate in which a first portion of a surface of the semiconductor substrate is recessed relative to a second portion of the surface of the semiconductor substrate to form a recessed region in the semiconductor substrate Albert Wu, Roawen Chen, Shiann-Ming Liou, Chien-Chuan Wei, Runzi Chang +2 more 2017-09-19
9391045 Recessed semiconductor substrates and associated techniques Albert Wu, Roawen Chen, Shiann-Ming Liou, Chien-Chuan Wei, Runzi Chang +2 more 2016-07-12
9257410 Package assembly including a semiconductor substrate in which a first portion of a surface of the semiconductor substrate is recessed relative to a second portion of the surface of the semiconductor substrate to form a recessed region in the semiconductor substrate Albert Wu, Roawen Chen, Shiann-Ming Liou, Chien-Chuan Wei, Runzi Chang +2 more 2016-02-09
9034730 Recessed semiconductor substrates and associated techniques Albert Wu, Roawen Chen, Shiann-Ming Liou, Chien-Chuan Wei, Runzi Chang +2 more 2015-05-19
8946890 Power/ground layout for chips Sehat Sutardja, Weidan Li, Shuhua Yu, Chuan-Cheng Cheng, Albert Wu 2015-02-03
8921938 Laterally diffused metal oxide semiconductor (LDMOS) device with overlapping wells Xin Zhang, Weidan Li, Chuan-Cheng Cheng, Jian-Hung Lee 2014-12-30
6127710 CMOS structure having a gate without spacers Jeong Yeol Choi, Chung-Jen Chien, Chuen-Der Lien 2000-10-03
6063676 Mosfet with raised source and drain regions Jeong Yeol Choi, Ken-Chuen Mui 2000-05-16
6043129 High density MOSFET with raised source and drain regions Jeong Yeol Choi, Ken-Chuen Mui 2000-03-28
6017785 Method for improving latch-up immunity and interwell isolation in a semiconductor device Jeong Yeol Choi, Cheun-Der Lien 2000-01-25
5831313 Structure for improving latch-up immunity and interwell isolation in a semiconductor device Jeong Yeol Choi, Cheun-Der Lien 1998-11-03
5793088 Structure for controlling threshold voltage of MOSFET Jeong Yeol Choi, Chung-Jen Chien, Chuen-Der Lien 1998-08-11
5750424 Method for fabricating a CMOS device Jeong Yeol Choi, Chung-Jen Chien, Chuen-Der Lien 1998-05-12
5654213 Method for fabricating a CMOS device Jeong Yeol Choi, Chung-Jen Chien, Chuen-Der Lien 1997-08-05