Issued Patents All Time
Showing 1–25 of 27 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7378289 | Method for forming photomask having test patterns in blading areas | Zhijian Ma, Pao-Lu Louis Huang, Pauli Hsueh | 2008-05-27 |
| 7316537 | Substrate transport apparatus | Joo Jib Park | 2008-01-08 |
| 7125775 | Method for forming hybrid device gates | Kuilong Wang, Tsengyou Syau | 2006-10-24 |
| 6898561 | Methods, apparatus and computer program products for modeling integrated circuit devices having reduced linewidths | Chunbo Liu, Zhijian Ma | 2005-05-24 |
| 6894356 | SRAM system having very lightly doped SRAM load transistors for improving SRAM cell stability and method for making the same | — | 2005-05-17 |
| 6496399 | Compact ternary content addressable memory cell | Sang-Yun Lee | 2002-12-17 |
| 6407008 | Method of forming an oxide layer | Yingbo Jia, Ohm-Guo Pan, Long Wang, Guo-Qiang Lo, Shih-Ked Lee | 2002-06-18 |
| 6258693 | Ion implantation for scalability of isolation in an integrated circuit | — | 2001-07-10 |
| 6191460 | Identical gate conductivity type static random access memory cell | Chuen-Der Lien | 2001-02-20 |
| 6165918 | Method for forming gate oxides of different thicknesses | James Yingbo Jia | 2000-12-26 |
| 6127710 | CMOS structure having a gate without spacers | Chung-Jen Chien, Chung Chyung Han, Chuen-Der Lien | 2000-10-03 |
| 6103555 | Method of improving the reliability of low-voltage programmable antifuse | — | 2000-08-15 |
| 6069054 | Method for forming isolation regions subsequent to gate formation and structure thereof | — | 2000-05-30 |
| 6063676 | Mosfet with raised source and drain regions | Chung Chyung Han, Ken-Chuen Mui | 2000-05-16 |
| 6043129 | High density MOSFET with raised source and drain regions | Chung Chyung Han, Ken-Chuen Mui | 2000-03-28 |
| 6017785 | Method for improving latch-up immunity and interwell isolation in a semiconductor device | Chung Chyung Han, Cheun-Der Lien | 2000-01-25 |
| 5926704 | Efficient method for fabricating P-wells and N-wells | Chuen-Der Lien | 1999-07-20 |
| 5888861 | Method of manufacturing a BiCMOS integrated circuit fully integrated within a CMOS process flow | Chung-Jen Chien, Chuen-Der Lien | 1999-03-30 |
| 5830789 | CMOS process forming wells after gate formation | Chuen-Der Lien | 1998-11-03 |
| 5831313 | Structure for improving latch-up immunity and interwell isolation in a semiconductor device | Chung Chyung Han, Cheun-Der Lien | 1998-11-03 |
| 5793088 | Structure for controlling threshold voltage of MOSFET | Chung-Jen Chien, Chung Chyung Han, Chuen-Der Lien | 1998-08-11 |
| 5780330 | Selective diffusion process for forming both n-type and p-type gates with a single masking step | — | 1998-07-14 |
| 5750424 | Method for fabricating a CMOS device | Chung-Jen Chien, Chung Chyung Han, Chuen-Der Lien | 1998-05-12 |
| 5679588 | Method for fabricating P-wells and N-wells having optimized field and active regions | Chuen-Der Lien | 1997-10-21 |
| 5654213 | Method for fabricating a CMOS device | Chung-Jen Chien, Chung Chyung Han, Chuen-Der Lien | 1997-08-05 |