Issued Patents All Time
Showing 25 most recent of 38 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12266542 | Atomic layer etching for subtractive metal etch | Wenbing Yang, Mohand Brouri, Samantha Tan, Yiwen FAN, Wook Choi +3 more | 2025-04-01 |
| 12249514 | Carbon based depositions used for critical dimension control during high aspect ratio feature etches and for forming protective layers | Jon Henri, Karthik S. Colinjivadi, Francis Sloan Roberts, Kapu Sirish Reddy, Samantha Tan +4 more | 2025-03-11 |
| 12062537 | High etch selectivity, low stress ashable carbon hard mask | Jun Xue, Mary Anne Manumpil, Samantha Tan | 2024-08-13 |
| 11935758 | Atomic layer etching for subtractive metal etch | Wenbing Yang, Mohand Brouri, Samantha Tan, Yiwen FAN, Wook Choi +3 more | 2024-03-19 |
| 11670516 | Metal-containing passivation for high aspect ratio etch | Karthik S. Colinjivadi, Samantha Tan, George Matamis, Yongsik Yu, Yang Pan +4 more | 2023-06-06 |
| 10340143 | Anodic aluminum oxide as hard mask for plasma etching | Chanyuan Liu | 2019-07-02 |
| 7921400 | Method for forming integrated circuit device using cell library with soft error resistant logic cells | Chuen-Der Lien | 2011-04-05 |
| 7582567 | Method for forming CMOS device with self-aligned contacts and region formed using salicide process | Tsengyou Syau, Chuen-Der Lien | 2009-09-01 |
| 7560800 | Die seal with reduced noise coupling | Chuen-Der Lien | 2009-07-14 |
| 7499303 | Binary and ternary non-volatile CAM | Chuen-Der Lien | 2009-03-03 |
| 7408751 | Self-biased electrostatic discharge protection method and circuit | Chuen-Der Lien | 2008-08-05 |
| 7400026 | Thin film resistor structure | Gaolong Jin, Wanqing Cao, Guo-Qiang Lo | 2008-07-15 |
| 7375392 | Gate structures having sidewall spacers formed using selective deposition | Chih-Hsiang Chen, Guo-Qiang Lo | 2008-05-20 |
| 7214990 | Memory cell with reduced soft error rate | Chuen-Der Lien, Louis Huang, Gaolong Jin, Wanqing Cao, Guo-Qiang Lo | 2007-05-08 |
| 7125783 | Dielectric anti-reflective coating surface treatment to prevent defect generation in associated wet clean | Guo-Qiang Lo, Ohm-Guo Pan, Zhenjiang Yu, Yu Mao, Tsengyou Syau | 2006-10-24 |
| 7098114 | Method for forming cmos device with self-aligned contacts and region formed using salicide process | Tsengyou Syau, Chuen-Der Lien | 2006-08-29 |
| 7078306 | Method for forming a thin film resistor structure | Gaolong Jin, Wanqing Cao, Guo-Qiang Lo | 2006-07-18 |
| 7067364 | Gate structures having sidewall spacers using selective deposition and method of forming the same | — | 2006-06-27 |
| 7042792 | Multi-port memory cells for use in FIFO applications that support data transfers between cache and supplemental memory arrays | Mario Au | 2006-05-09 |
| 7015116 | Stress-relieved shallow trench isolation (STI) structure and method for forming the same | Guo-Qiang Lo, Brian Schorr, Gary Foley | 2006-03-21 |
| 6872668 | Multi-step tungsten etchback process to preserve barrier integrity in an integrated circuit structure | Wanqing Cao, Guo-Qiang Lo, Hongyong Xue | 2005-03-29 |
| 6791155 | Stress-relieved shallow trench isolation (STI) structure and method for forming the same | Guo-Qiang Lo, Brian Schorr, Gary Foley | 2004-09-14 |
| 6627543 | Low-temperature sputtering system and method for salicide process | Wanqing Cao, Guo-Qiang Lo, Robert B. Hixson, Eric Lee | 2003-09-30 |
| 6566236 | Gate structures with increased etch margin for self-aligned contact and the method of forming the same | Tsengyou Syau, Guo-Qiang Lo, Chuen-Der Lien, Sang-Yun Lee, Ching-Kai Lin | 2003-05-20 |
| 6534414 | Dual-mask etch of dual-poly gate in CMOS processing | Kuilong Wang, Tsengyou Syau, Chuen-Der Lien | 2003-03-18 |