Issued Patents All Time
Showing 25 most recent of 32 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8230174 | Multi-queue address generator for start and end addresses in a multi-queue first-in first-out memory system | Jason Z. Mo, Xiaoping Fang | 2012-07-24 |
| 7945716 | Serial buffer supporting virtual queue to physical memory mapping | Chi-Lie Wang, Calvin Nguyen | 2011-05-17 |
| 7870310 | Multiple counters to relieve flag restriction in a multi-queue first-in first-out memory system | Jason Z. Mo | 2011-01-11 |
| 7805552 | Partial packet write and write data filtering in a multi-queue first-in first-out memory system | Jason Z. Mo, Hui Su | 2010-09-28 |
| 7805551 | Multi-function queue to support data offload, protocol translation and pass-through FIFO | Chi-Lie Wang, Jason Z. Mo | 2010-09-28 |
| 7586343 | Output drive circuit that accommodates variable supply voltages | David J. Pilling, Kar-chung Leo Lee | 2009-09-08 |
| 7554379 | High-speed, low-power level shifter for mixed signal-level environments | David J. Pilling | 2009-06-30 |
| 7523232 | Mark/re-read and mark/re-write operations in a multi-queue first-in first-out memory system | Jason Z. Mo | 2009-04-21 |
| 7392354 | Multi-queue FIFO memory devices that support a backed-off standard mode of operation and methods of operating same | Jason Z. Mo | 2008-06-24 |
| 7269700 | Status bus accessing only available quadrants during loop mode operation in a multi-queue first-in first-out memory system | Jason Z. Mo, Cheng-Han Wu | 2007-09-11 |
| 7257687 | Synchronization of active flag and status bus flags in a multi-queue first-in first-out memory system | Jason Z. Mo, Cheng-Han Wu | 2007-08-14 |
| 7246300 | Sequential flow-control and FIFO memory devices having error detection and correction capability with diagnostic bit generation | Jiann-Jeng Duh | 2007-07-17 |
| 7224195 | Output drive circuit that accommodates variable supply voltages | David J. Pilling, Kar-chung Leo Lee | 2007-05-29 |
| 7209983 | Sequential flow-control and FIFO memory devices that are depth expandable in standard mode operation | Jiann-Jeng Duh, Tze-yuan Fang | 2007-04-24 |
| 7158440 | FIFO memory devices having write and read control circuits that support x4N, x2N and xN data widths during DDR and SDR modes of operation | Jiann-Jeng Duh | 2007-01-02 |
| 7154327 | Self-timed multiple blanking for noise suppression during flag generation in a multi-queue first-in first-out memory system | Jason Z. Mo | 2006-12-26 |
| 7099231 | Interleaving memory blocks to relieve timing bottleneck in a multi-queue first-in first-out memory system | Jason Z. Mo, Ta-Chung Ma, Lan Lin | 2006-08-29 |
| 7093047 | Integrated circuit memory devices having clock signal arbitration circuits therein and methods of performing clock signal arbitration | Jiann-Jeng Duh | 2006-08-15 |
| 7082071 | Integrated DDR/SDR flow control managers that support multiple queues and MUX, DEMUX and broadcast operating modes | Roland T. Knaack, David Gibson, Mario Montana, Stewart Speed, Srinivas Satish Babu Bamdhamravuri +1 more | 2006-07-25 |
| 7076610 | FIFO memory devices having multi-port cache memory arrays therein that support hidden EDC latency and bus matching and methods of operating same | Jiann-Jeng Duh | 2006-07-11 |
| 7042792 | Multi-port memory cells for use in FIFO applications that support data transfers between cache and supplemental memory arrays | Shih-Ked Lee | 2006-05-09 |
| 6874064 | FIFO memory devices having multi-port cache and extended capacity memory devices therein with retransmit capability | Li-Yuan Chen | 2005-03-29 |
| 6795360 | Fifo memory devices that support all four combinations of DDR or SDR write modes with DDR or SDR read modes | Jiann-Jeng Duh | 2004-09-21 |
| 6778454 | FIFO memory devices that support all combinations of DDR and SDR read and write modes | Jiann-Jeng Duh | 2004-08-17 |
| 6754777 | FIFO memory devices and methods of operating FIFO memory devices having multi-port cache memory devices therein | Li-Yuan Chen | 2004-06-22 |