Issued Patents All Time
Showing 1–8 of 8 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7710789 | Synchronous address and data multiplexed mode for SRAM | Tzong-Kwang Henry Yeh, Casey Springer | 2010-05-04 |
| 7246300 | Sequential flow-control and FIFO memory devices having error detection and correction capability with diagnostic bit generation | Mario Au | 2007-07-17 |
| 7209983 | Sequential flow-control and FIFO memory devices that are depth expandable in standard mode operation | Mario Au, Tze-yuan Fang | 2007-04-24 |
| 7158440 | FIFO memory devices having write and read control circuits that support x4N, x2N and xN data widths during DDR and SDR modes of operation | Mario Au | 2007-01-02 |
| 7093047 | Integrated circuit memory devices having clock signal arbitration circuits therein and methods of performing clock signal arbitration | Mario Au | 2006-08-15 |
| 7076610 | FIFO memory devices having multi-port cache memory arrays therein that support hidden EDC latency and bus matching and methods of operating same | Mario Au | 2006-07-11 |
| 6795360 | Fifo memory devices that support all four combinations of DDR or SDR write modes with DDR or SDR read modes | Mario Au | 2004-09-21 |
| 6778454 | FIFO memory devices that support all combinations of DDR and SDR read and write modes | Mario Au | 2004-08-17 |