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Timing controllers having partitioned pipelined delay chains therein |
Bruce Lorenz Chin |
2015-01-27 |
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Multiple time domain synchronizer circuits |
Bruce Lorenz Chin |
2014-09-02 |
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System and method for arbitration using availability signals |
— |
2012-10-16 |
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System and method for arbitration of multicast data packets using holds |
— |
2010-08-24 |
| 7706387 |
System and method for round robin arbitration |
— |
2010-04-27 |
| 7684431 |
System and method for arbitration in a packet switch |
— |
2010-03-23 |
| 7120075 |
Multi-FIFO integrated circuit devices that support multi-queue operating modes with enhanced write path and read path queue switching |
Roland T. Knaack |
2006-10-10 |
| 7110321 |
Multi-bank integrated circuit memory devices having high-speed memory access timing |
— |
2006-09-19 |
| 7082071 |
Integrated DDR/SDR flow control managers that support multiple queues and MUX, DEMUX and broadcast operating modes |
Roland T. Knaack, Mario Montana, Mario Au, Stewart Speed, Srinivas Satish Babu Bamdhamravuri +1 more |
2006-07-25 |
| 6972998 |
Double data rate memory devices including clock domain alignment circuits and methods of operation thereof |
Angus David Starr MacAdam, Mike Farrell |
2005-12-06 |
| 4548045 |
Method for continuously producing pop-shaped frozen confections |
Romulo A. Altares, Michael A. Goyda, Joseph L. Hegadorn, Virendra N. Kapoor |
1985-10-22 |