Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Double data rate memory devices including clock domain alignment circuits and methods of operation thereof

Double data rate memory devices including clock domain alignment circuits and methods of operation thereof

US Patent 6972998 · Granted Dec 6, 2005

Estimated economic value: $10,014,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Remote monitoring system2019
Method of analyzing chromosomal inversions2017
Timing controllers having partitioned pipelined delay chains therein2015
Multiple time domain synchronizer circuits2014
System and method for arbitration using availability signals2012
Old virtual queues technique for routing data packets in a packet switch2011
Packet switch with port route tables2011
Packet latency based arbitration technique for a packet switch2011
Packet switch with configurable virtual channels2011
Power reduction technique for buffered crossbar switch2011
System and method of constructing data packets in a packet switch2010
Packet switch with configurable bandwidth allocation precision2010