Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › FIFO memory devices that support all combinations of DDR and SDR read and write modes

FIFO memory devices that support all combinations of DDR and SDR read and write modes

US Patent 6778454 · Granted Aug 17, 2004

Estimated economic value: $13,447,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Multi-queue address generator for start and end addresses in a multi-queue first2012
Serial buffer supporting virtual queue to physical memory mapping2011
Multiple counters to relieve flag restriction in a multi-queue first-in first-ou2011
Multi-function queue to support data offload, protocol translation and pass-thro2010
Partial packet write and write data filtering in a multi-queue first-in first-ou2010
Synchronous address and data multiplexed mode for SRAM2010
Output drive circuit that accommodates variable supply voltages2009
High-speed, low-power level shifter for mixed signal-level environments2009
Mark/re-read and mark/re-write operations in a multi-queue first-in first-out me2009
Multi-queue FIFO memory devices that support a backed-off standard mode of opera2008
Status bus accessing only available quadrants during loop mode operation in a mu2007
Synchronization of active flag and status bus flags in a multi-queue first-in fi2007