Issued Patents All Time
Showing 1–23 of 23 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8863053 | Intelligent timing analysis and constraint generation GUI | Martin J. Fennell, Matthias Dinter | 2014-10-14 |
| 8584068 | Timing violation debugging inside place and route tool | Matthias Dinter, Herbert Johannes Preuthen | 2013-11-12 |
| 8572543 | Automation of tie cell insertion, optimization and replacement by scan flip-flops to increase fault coverage | Matthias Dinter, Ralf Leuchter | 2013-10-29 |
| 8564337 | Clock tree insertion delay independent interface | Stefan G. Block, Herbert Johannes Preuthen | 2013-10-22 |
| 8539407 | Intelligent timing analysis and constraint generation GUI | Martin J. Fennell, Matthias Dinter | 2013-09-17 |
| 8332801 | Special engineering change order cells | Matthias Dinter, Johann Leyrer | 2012-12-11 |
| 8219959 | Generating integrated circuit floorplan layouts | Norbert Mueller, Stefan G. Block | 2012-07-10 |
| 8161447 | Automation of tie cell insertion, optimization and replacement by scan flip-flops to increase fault coverage | Matthias Dinter, Ralf Leuchter | 2012-04-17 |
| 7975197 | On-chip scan clock generator for ASIC testing | Iain Clark | 2011-07-05 |
| 7958473 | Method and computer program for configuring an integrated circuit design for static timing analysis | Udo Elsholz, Stephan Habel, Ansgar Bambynek | 2011-06-07 |
| 7747975 | Timing violation debugging inside place and route tool | Matthias Dinter, Herbert Johannes Preuthen | 2010-06-29 |
| 7634748 | Special engineering change order cells | Matthias Dinter, Johann Leyrer | 2009-12-15 |
| 7546560 | Optimization of flip flop initialization structures with respect to design size and design closure effort from RTL to netlist | Martin J. Fennell, Iain Stickland | 2009-06-09 |
| 7546568 | Automation of tie cell insertion, optimization and replacement by scan flip-flops to increase fault coverage | Matthias Dinter, Ralf Leuchter | 2009-06-09 |
| 7523426 | Intelligent timing analysis and constraint generation GUI | Martin J. Fennell, Matthias Dinter | 2009-04-21 |
| 7441210 | On-the-fly RTL instructor for advanced DFT and design closure | Juergen Lahner, Balamurugan Balasubramanian | 2008-10-21 |
| 7398489 | Advanced standard cell power connection | Matthias Dinter, Herbert Johannes Preuthen | 2008-07-08 |
| 7334206 | Cell builder for different layer stacks | Matthias Dinter, Roland Klemt | 2008-02-19 |
| 7331028 | Engineering change order scenario manager | Matthias Dinter, Herbert Johannes Preuthen | 2008-02-12 |
| 7325215 | Timing violation debugging inside place and route tool | Matthias Dinter, Herbert Johannes Preuthen | 2008-01-29 |
| 7191424 | Special tie-high/low cells for single metal layer route changes | Norbert Mueller, Ralf Leuchter | 2007-03-13 |
| 7117472 | Placement of a clock signal supply network during design of integrated circuits | Stefan Auracher, Claus Pribbernow, Andreas Hils, Manisha R. Patel, James Imper | 2006-10-03 |
| 7000163 | Optimized buffering for JTAG boundary scan nets | Juergen Lahner, Ludger F. Johanterwage, Benjamin Mbouombouo, Human Boluki, Weidan Li | 2006-02-14 |