MD

Matthias Dinter

LS Lsi: 10 patents #118 of 1,740Top 7%
Lsi Logic: 3 patents #574 of 1,957Top 30%
AP Avago Technologies General Ip (Singapore) Pte.: 1 patents #883 of 2,004Top 45%
Overall (All Time): #352,717 of 4,157,543Top 9%
14
Patents All Time

Issued Patents All Time

Patent #TitleCo-InventorsDate
8863053 Intelligent timing analysis and constraint generation GUI Juergen Dirks, Martin J. Fennell 2014-10-14
8584068 Timing violation debugging inside place and route tool Juergen Dirks, Herbert Johannes Preuthen 2013-11-12
8572543 Automation of tie cell insertion, optimization and replacement by scan flip-flops to increase fault coverage Juergen Dirks, Ralf Leuchter 2013-10-29
8539407 Intelligent timing analysis and constraint generation GUI Juergen Dirks, Martin J. Fennell 2013-09-17
8332801 Special engineering change order cells Juergen Dirks, Johann Leyrer 2012-12-11
8161447 Automation of tie cell insertion, optimization and replacement by scan flip-flops to increase fault coverage Juergen Dirks, Ralf Leuchter 2012-04-17
7747975 Timing violation debugging inside place and route tool Juergen Dirks, Herbert Johannes Preuthen 2010-06-29
7634748 Special engineering change order cells Juergen Dirks, Johann Leyrer 2009-12-15
7546568 Automation of tie cell insertion, optimization and replacement by scan flip-flops to increase fault coverage Juergen Dirks, Ralf Leuchter 2009-06-09
7523426 Intelligent timing analysis and constraint generation GUI Juergen Dirks, Martin J. Fennell 2009-04-21
7398489 Advanced standard cell power connection Juergen Dirks, Herbert Johannes Preuthen 2008-07-08
7334206 Cell builder for different layer stacks Juergen Dirks, Roland Klemt 2008-02-19
7331028 Engineering change order scenario manager Juergen Dirks, Herbert Johannes Preuthen 2008-02-12
7325215 Timing violation debugging inside place and route tool Juergen Dirks, Herbert Johannes Preuthen 2008-01-29