Issued Patents All Time
Showing 26–50 of 117 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6420220 | Method of forming electrode for high performance semiconductor devices | Mark I. Gardner, H. Jim Fulford | 2002-07-16 |
| 6410967 | Transistor having enhanced metal silicide and a self-aligned gate electrode | Frederick N. Hause, Mark I. Gardner | 2002-06-25 |
| 6403445 | Enhanced trench isolation structure | Mark I. Gardner, Frederick N. Hause | 2002-06-11 |
| 6362510 | Semiconductor topography having improved active device isolation and reduced dopant migration | Mark I. Gardner, H. Jim Fulford | 2002-03-26 |
| 6348413 | High pressure N2 RTA process for TiS2 formation | Timothy Z. Hossain | 2002-02-19 |
| 6338992 | Programmable read only memory in CMOS process flow | Shafqat Ahmed, Hemanshu Bhatt, Robindranath Banerjee | 2002-01-15 |
| 6323519 | Ultrathin, nitrogen-containing MOSFET sidewall spacers using low-temperature semiconductor fabrication process | Mark I. Gardner, Derick J. Wristers | 2001-11-27 |
| 6323524 | Semiconductor device having a vertical active region and method of manufacture thereof | Robert Dawson | 2001-11-27 |
| 6323561 | Spacer formation for precise salicide formation | Mark I. Gardner, Fred N. Hause | 2001-11-27 |
| 6303962 | Dielectrically-isolated transistor with low-resistance metal source and drain formed using sacrificial source and drain structures | Mark I. Gardner, H. Jim Fulford | 2001-10-16 |
| 6294397 | Drop-in test structure and abbreviated integrated circuit process flow for characterizing production integrated circuit process flow, topography, and equipment | Richard W. Jarvis, Iraj Emami | 2001-09-25 |
| 6281132 | Device and method for etching nitride spacers formed upon an integrated circuit gate conductor | Thien T. Nguyen, Mark I. Gardner | 2001-08-28 |
| 6274442 | Transistor having a nitrogen incorporated epitaxially grown gate dielectric and method of making same | Mark I. Gardner, H. Jim Fulford | 2001-08-14 |
| 6268634 | Transistor with an ultra short channel length defined by a laterally diffused nitrogen implant | Mark I. Gardner, H. Jim Eulford, Jr. | 2001-07-31 |
| 6268637 | Method of making air gap isolation by making a lateral EPI bridge for low K isolation advanced CMOS fabrication | Mark I. Gardner, Frederick N. Hause | 2001-07-31 |
| 6261909 | Semiconductor device having ultra shallow junctions and a reduced channel length and method for making same | Mark I. Gardner, H. Jim Fulford | 2001-07-17 |
| 6261908 | Buried local interconnect | Frederick N. Hause, Mark I. Gardner | 2001-07-17 |
| 6255215 | Semiconductor device having silicide layers formed using a collimated metal layer | Fred N. Hause, William S. Brennan | 2001-07-03 |
| 6251800 | Ultrathin deposited gate dielectric formation using low-power, low-pressure PECVD for improved semiconductor device performance | Sey-Ping Sun, Mark I. Gardner | 2001-06-26 |
| 6249032 | Semiconductor device having patterned metal layer over a polysilicon line and method of fabrication thereof | Homi E. Nariman, H. Jim Fulford | 2001-06-19 |
| 6245638 | Trench and gate dielectric formation for semiconductor devices | Mark I. Gardner, H. Jim Fulford | 2001-06-12 |
| 6242317 | High quality isolation structure formation | Mark I. Gardner, Thien T. Nguyen | 2001-06-05 |
| 6242273 | Fractal filter applied to a contamination-free manufacturing signal to improve signal-to-noise ratios | Thomas J. Goodwin, Iraj Emami | 2001-06-05 |
| 6225168 | Semiconductor device having metal gate electrode and titanium or tantalum nitride gate dielectric barrier layer and process of fabrication thereof | Mark I. Gardner, H. Jim Fulford, Fred N. Hause, Dim-Lee Kwong | 2001-05-01 |
| 6222230 | Method of making an elevated source/drain with enhanced graded sidewalls for transistor scaling integrated with spacer formation | Mark I. Gardner, H. Jim Fulford | 2001-04-24 |