Issued Patents All Time
Showing 76–100 of 117 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6127235 | Method for making asymmetrical gate oxide thickness in channel MOSFET region | Mark I. Gardner, H. James Fulford | 2000-10-03 |
| 6117763 | Method of manufacturing a semiconductor device with a low permittivity dielectric layer and contamination due to exposure to water | Robin Cheung | 2000-09-12 |
| 6117739 | Semiconductor device with layered doped regions and methods of manufacture | Mark I. Gardner, Fred N. Hause | 2000-09-12 |
| 6114229 | Polysilicon gate electrode critical dimension and drive current control in MOS transistor fabrication | Frederick N. Hause, Mark I. Gardner | 2000-09-05 |
| 6100173 | Forming a self-aligned silicide gate conductor to a greater thickness than junction silicide structures using a dual-salicidation process | Mark I. Gardner, H. Jim Fulford | 2000-08-08 |
| 6096643 | Method of fabricating a semiconductor device having polysilicon line with extended silicide layer | Homi E. Nariman, H. Jim Fulford | 2000-08-01 |
| 6090676 | Process for making high performance MOSFET with scaled gate electrode thickness | Mark I. Gardner, H. Jim Fulford | 2000-07-18 |
| 6090694 | Local interconnect patterning and contact formation | Fred N. Hause, Mark I. Gardner | 2000-07-18 |
| 6087705 | Trench isolation structure partially bound between a pair of low K dielectric structures | Mark I. Gardner, H. Jim Fulford | 2000-07-11 |
| 6084280 | Transistor having a metal silicide self-aligned to the gate | Mark I. Gardner, Frederick N. Hause | 2000-07-04 |
| 6080676 | Device and method for etching spacers formed upon an integrated circuit gate conductor | Thien T. Nguyen, Mark I. Gardner | 2000-06-27 |
| 6077749 | Method of making dual channel gate oxide thickness for MOSFET transistor design | Mark I. Gardner, H. Jim Fulford | 2000-06-20 |
| 6078078 | V-gate transistor | Mark I. Gardner, H. Jim Fulford | 2000-06-20 |
| 6071749 | Process for forming a semiconductor device with controlled relative thicknesses of the active region and gate electrode | Robert Dawson | 2000-06-06 |
| 6067154 | Method and apparatus for the molecular identification of defects in semiconductor manufacturing using a radiation scattering technique such as raman spectroscopy | Tim Z. Hossain | 2000-05-23 |
| 6063679 | Spacer formation for graded dopant profile having a triangular geometry | Mark I. Gardner, Fred N. Hause | 2000-05-16 |
| 6051863 | Transistor gate conductor having sidewall surfaces upon which a spacer having a profile that substantially prevents silicide bridging is formed | Fred N. Hause, Mark I. Gardner | 2000-04-18 |
| 6046089 | Selectively sized spacers | Mark I. Gardner, Fred N. Hause | 2000-04-04 |
| 6044203 | Rapid thermal anneal system and method including improved temperature sensing and monitoring | Robert Dawson, Frederick N. Hause | 2000-03-28 |
| 6037607 | Structure for testing junction leakage of salicided devices fabricated using shallow trench and refill techniques | Frederick N. Hause, Robert Dawson | 2000-03-14 |
| 6033921 | Method for depositing a material of controlled, variable thickness across a surface for planarization of that surface | Robert Dawson | 2000-03-07 |
| 6030875 | Method for making semiconductor device having nitrogen-rich active region-channel interface | Robert Dawson, Michael Duane | 2000-02-29 |
| 6008109 | Trench isolation structure having a low K dielectric encapsulated by oxide | H. Jim Fulford, Mark I. Gardner | 1999-12-28 |
| 6008095 | Process for formation of isolation trenches with high-K gate dielectrics | Mark I. Gardner, H. Jim Fulford | 1999-12-28 |
| 6005285 | Argon doped epitaxial layers for inhibiting punchthrough within a semiconductor device | Mark I. Gardner, H. Jim Fulford | 1999-12-21 |