Issued Patents All Time
Showing 51–75 of 117 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6210999 | Method and test structure for low-temperature integration of high dielectric constant gate dielectrics into self-aligned semiconductor devices | Mark I. Gardner, John L. Nistler | 2001-04-03 |
| 6207485 | Integration of high K spacers for dual gate oxide channel fabrication technique | Mark I. Gardner, H. James Fulford | 2001-03-27 |
| 6207544 | Method of fabricating ultra thin nitride spacers and device incorporating same | Thien T. Nguyen, Mark I. Gardner | 2001-03-27 |
| 6204153 | Argon doped epitaxial layers for inhibiting punchthrough within a semiconductor device | Mark I. Gardner, H. Jim Fulford | 2001-03-20 |
| 6194768 | High dielectric constant gate dielectric with an overlying tantalum gate conductor formed on a sidewall surface of a sacrificial structure | Mark I. Gardner, Frederick N. Hause | 2001-02-27 |
| 6188106 | MOSFET having a highly doped channel liner and a dopant seal to provide enhanced device properties | Mark I. Gardner, H. Jim Fulford | 2001-02-13 |
| 6184986 | Depositing a material of controlled, variable thickness across a surface for planarization of that surface | Robert Dawson | 2001-02-06 |
| 6169006 | Semiconductor device having grown oxide spacers and method of manufacture thereof | Mark I. Gardner, H. Jim Fulford | 2001-01-02 |
| 6168958 | Semiconductor structure having multiple thicknesses of high-K gate dielectrics and process of manufacture therefor | Mark I. Gardner, H. Jim Fulford | 2001-01-02 |
| 6162687 | Method of manufacturing semiconductor device having oxide-nitride gate insulating layer | Mark I. Gardner, H. Jim Fulford | 2000-12-19 |
| 6159804 | Disposable sidewall oxidation fabrication method for making a transistor having an ultra short channel length | Mark I. Gardner, H. Jim Fulford | 2000-12-12 |
| 6160300 | Multi-layer gate conductor having a diffusion barrier in the bottom layer | Mark I. Gardner, Derick J. Wristers | 2000-12-12 |
| 6159814 | Spacer formation by poly stack dopant profile design | Mark I. Gardner, Fred N. Hause | 2000-12-12 |
| 6156649 | Method of forming uniform sheet resistivity salicide | Fred N. Hause, Robert Dawson | 2000-12-05 |
| 6150222 | Method of making a high performance transistor with elevated spacer formation and self-aligned channel regions | Mark I. Gardner, Thien T. Nguyen | 2000-11-21 |
| 6151119 | Apparatus and method for determining depth profile characteristics of a dopant material in a semiconductor device | Alan Campion, Tim Z. Hossain | 2000-11-21 |
| 6150708 | Advanced CMOS circuitry that utilizes both sides of a wafer surface for increased circuit density | Mark I. Gardner, H. Jim Fulford | 2000-11-21 |
| 6146983 | Method of making semiconductor device having sacrificial salicidation layer | Mark I. Gardner, Frederick N. Hause | 2000-11-14 |
| 6146952 | Semiconductor device having self-aligned asymmetric source/drain regions and method of fabrication thereof | Homi E. Nariman, H. Jim Fulford | 2000-11-14 |
| 6144071 | Ultrathin silicon nitride containing sidewall spacers for improved transistor performance | Mark I. Gardner, H. Jim Fulford | 2000-11-07 |
| 6140691 | Trench isolation structure having a low K dielectric material isolated from a silicon-based substrate | Mark I. Gardner, H. Jim Fulford | 2000-10-31 |
| 6140674 | Buried trench capacitor | Frederick N. Hause, Mark I. Gardner | 2000-10-31 |
| 6130012 | Ion beam milling to generate custom reticles | Thomas J. Goodwin | 2000-10-10 |
| 6127251 | Semiconductor device with a reduced width gate dielectric and method of making same | Mark I. Gardener, Frederick N. Hause | 2000-10-03 |
| 6127234 | Ultra shallow extension formation using disposable spacers | Mark I. Gardner, Frederick N. Hause | 2000-10-03 |