Issued Patents All Time
Showing 1–11 of 11 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7460922 | Scanner optimization for reduced across-chip performance variation through non-contact electrical metrology | Bhanwar Singh, Jason P. Cain, Harish K. Bolla | 2008-12-02 |
| 7373215 | Transistor gate shape metrology using multiple data sources | Jason P. Cain, Bhanwar Singh | 2008-05-13 |
| 7334202 | Optimizing critical dimension uniformity utilizing a resist bake plate simulator | Bhanwar Singh, Qiaolin Zhang, Joyce S. Oey Hewett, Luigi Capodiece | 2008-02-19 |
| 7221060 | Composite alignment mark scheme for multi-layers in lithography | Bhanwar Singh, Khoi A. Phan, Bharath Rangarajan, Ramkumar Subramanian | 2007-05-22 |
| 7158896 | Real time immersion medium control using scatterometry | Bhanwar Singh, Srikanteswara Dakshina-Murthy, Khoi A. Phan, Ramkumar Subramanian, Bharath Rangarajan | 2007-01-02 |
| 6560504 | Use of contamination-free manufacturing data in fault detection and classification as well as in run-to-run control | Thomas J. Goodwin, Charles E. May | 2003-05-06 |
| 6452412 | Drop-in test structure and methodology for characterizing an integrated circuit process flow and topography | Richard W. Jarvis, Charles E. May | 2002-09-17 |
| 6297644 | Multipurpose defect test structure with switchable voltage contrast capability and method of use | Richard W. Jarvis, John L. Nistler, Michael G. McIntyre | 2001-10-02 |
| 6294397 | Drop-in test structure and abbreviated integrated circuit process flow for characterizing production integrated circuit process flow, topography, and equipment | Richard W. Jarvis, Charles E. May | 2001-09-25 |
| 6268717 | Semiconductor test structure with intentional partial defects and method of use | Richard W. Jarvis, Alan Bruce Berezin | 2001-07-31 |
| 6242273 | Fractal filter applied to a contamination-free manufacturing signal to improve signal-to-noise ratios | Thomas J. Goodwin, Charles E. May | 2001-06-05 |