Issued Patents All Time
Showing 51–75 of 141 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6054356 | Transistor and process of making a transistor having an improved LDD masking material | Robert Dawson, Mark W. Michael | 2000-04-25 |
| 6051863 | Transistor gate conductor having sidewall surfaces upon which a spacer having a profile that substantially prevents silicide bridging is formed | Mark I. Gardner, Charles E. May | 2000-04-18 |
| 6049134 | Mask generation technique for producing an integrated circuit with optimal metal interconnect layout for achieving global planarization | Mark W. Michael, Robert Dawson, Basab Bandyopadhyay, H. Jim Fulford, William S. Brennan | 2000-04-11 |
| 6049133 | Semiconductor fabrication employing concurrent diffusion barrier and salicide formation | Mark I. Gardner | 2000-04-11 |
| 6046471 | Ultra shallow junction depth transistors | Mark I. Gardner, Daniel Kadosh | 2000-04-04 |
| 6046089 | Selectively sized spacers | Mark I. Gardner, Charles E. May | 2000-04-04 |
| 6043533 | Method of integrating Ldd implantation for CMOS device fabrication | Mark I. Gardner, Robert Paiz | 2000-03-28 |
| 6031289 | Integrated circuit which uses a recessed local conductor for producing staggered interconnect lines | H. Jim Fulford, Basab Bandyopadhyay, Robert Dawson, Mark W. Michael, William S. Brennan | 2000-02-29 |
| 6027859 | Semiconductor substrate having extended scribe line test structure and method of fabrication thereof | Robert Dawson, Mark W. Michael | 2000-02-22 |
| 6018179 | Transistors having a scaled channel length and integrated spacers with enhanced silicidation properties | Mark I. Gardner, Derick J. Wristers | 2000-01-25 |
| 6013574 | Method of forming low resistance contact structures in vias arranged between two levels of interconnect lines | Michael J. Gatto, Kuang-Yeh Chang | 2000-01-11 |
| 5998293 | Multilevel interconnect structure of an integrated circuit having air gaps and pillars separating levels of interconnect | Robert Dawson, Mark W. Michael, William S. Brennan, Basab Bandyopadhyay, H. Jim Fulford | 1999-12-07 |
| 5994779 | Semiconductor fabrication employing a spacer metallization technique | Mark I. Gardner, Daniel Kadosh | 1999-11-30 |
| 5989964 | Post-spacer LDD implant for shallow LDD transistor | Mark I. Gardner | 1999-11-23 |
| 5981357 | Semiconductor trench isolation with improved planarization methodology | Robert Dawson, Charles E. May, Mark I. Gardner, Kuang-Yeh Chang | 1999-11-09 |
| 5981354 | Semiconductor fabrication employing a flowable oxide to enhance planarization in a shallow trench isolation process | Thomas E. Spikes, Jr., Daniel Kadosh | 1999-11-09 |
| 5970354 | Poly recessed fabrication method for defining high performance MOSFETS | Mark I. Gardner, H. Jim Fulford | 1999-10-19 |
| 5968843 | Method of planarizing a semiconductor topography using multiple polish pads | Robert Dawson, H. Jim Fulford, Basab Bandyopadhyay, Mark W. Michael, William S. Brennan | 1999-10-19 |
| 5963783 | In-line detection and assessment of net charge in PECVD silicon dioxide (oxide) layers | John K. Lowell, Robert Dawson | 1999-10-05 |
| 5962914 | Reduced bird's beak field oxidation process using nitrogen implanted into active region | Mark I. Gardner, Kuang-Yeh Chang | 1999-10-05 |
| 5955785 | Copper-containing plug for connection of semiconductor surface with overlying conductor | Mark I. Gardner | 1999-09-21 |
| 5952702 | High performance MOSFET structure having asymmetrical spacer formation and having source and drain regions with different doping concentration | Mark I. Gardner | 1999-09-14 |
| 5953626 | Dissolvable dielectric method | Basab Bandyopadhyay, Robert Dawson, H. Jim Fulford, Mark W. Michael, William S. Brennan | 1999-09-14 |
| 5949126 | Trench isolation structure employing protective sidewall spacers upon exposed surfaces of the isolation trench | Robert Dawson, Charles E. May | 1999-09-07 |
| 5946579 | Stacked mask integration technique for advanced CMOS transistor formation | H. Jim Fulford, Mark I. Gardner | 1999-08-31 |