Issued Patents All Time
Showing 101–125 of 141 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 5854131 | Integrated circuit having horizontally and vertically offset interconnect lines | Robert Dawson, Mark W. Michael, Basab Bandyopadhyay, H. Jim Fulford Jr., William S. Brennan | 1998-12-29 |
| 5851921 | Semiconductor device and method for forming the device using a dual layer, self-aligned silicide to enhance contact performance | Mark I. Gardner | 1998-12-22 |
| 5851913 | Method for forming a multilevel interconnect structure of an integrated circuit by a single via etch and single fill process | William S. Brennan, Robert Dawson, H. Jim Fulford, Basab Bandyopadhyay, Mark W. Michael | 1998-12-22 |
| 5851883 | High density integrated circuit process | Mark I. Gardner, Daniel Kadosh | 1998-12-22 |
| 5850105 | Substantially planar semiconductor topography using dielectrics and chemical mechanical polish | Robert Dawson, Mark W. Michael, Basab Bandyopadhyay, H. Jim Fulford, William S. Brennan | 1998-12-15 |
| 5849621 | Method and structure for isolating semiconductor devices after transistor formation | Mark I. Gardner, H. Jim Fulford | 1998-12-15 |
| 5846876 | Integrated circuit which uses a damascene process for producing staggered interconnect lines | Basab Bandyopadhyay, H. Jim Fulford, Robert Dawson, Mark W. Michael, William S. Brennan | 1998-12-08 |
| 5847462 | Integrated circuit having conductors of enhanced cross-sectional area with etch stop barrier layer | Basab Bandyopadhyay, H. Jim Fulford, William S. Brennan, Robert Dawson, Mark W. Michael | 1998-12-08 |
| 5843625 | Method of reducing via and contact dimensions beyond photolithography equipment limits | Mark I. Gardner, Robert Dawson | 1998-12-01 |
| 5841168 | High performance asymmetrical MOSFET structure and method of making the same | Mark I. Gardner, Daniel Kadosh | 1998-11-24 |
| 5837572 | CMOS integrated circuit formed by using removable spacers to produce asymmetrical NMOS junctions before asymmetrical PMOS junctions for optimizing thermal diffusivity of dopants implanted therein | Mark I. Gardner, H. Jim Fulford | 1998-11-17 |
| 5830773 | Method for forming semiconductor field region dielectrics having globally planarized upper surfaces | William S. Brennan, Robert Dawson, Basab Bandyopadhyay, H. Jim Fulford, Mark W. Michael | 1998-11-03 |
| 5827776 | Method of making an integrated circuit which uses an etch stop for producing staggered interconnect lines | Basab Bandyopadhyay, H. Jim Fulford, Robert Dawson, Mark W. Michael, William S. Brennan | 1998-10-27 |
| 5827763 | Method of forming a multiple transistor channel doping using a dual resist fabrication sequence | Mark I. Gardner | 1998-10-27 |
| 5821146 | Method of fabricating FET or CMOS transistors using MeV implantation | Kuang-Yeh Chang, Yowjuang W. Liu, Mark I. Gardner | 1998-10-13 |
| 5817560 | Ultra short trench transistors and process for making same | Mark I. Gardner | 1998-10-06 |
| 5814555 | Interlevel dielectric with air gaps to lessen capacitive coupling | Basab Bandyopadhyay, H. Jim Fulford, Robert Dawson, Mark W. Michael, William S. Brennan | 1998-09-29 |
| 5811347 | Nitrogenated trench liner for improved shallow trench isolation | Mark I. Gardner, Kuang-Yeh Chang | 1998-09-22 |
| 5804497 | Selectively doped channel region for increased I.sub.Dsat and method for making same | Mark I. Gardner, H. Jim Fulford | 1998-09-08 |
| 5793089 | Graded MOS transistor junction formed by aligning a sequence of implants to a selectively removable polysilicon sidewall space and oxide thermally grown thereon | H. Jim Fulford, Mark I. Gardner | 1998-08-11 |
| 5793090 | Integrated circuit having multiple LDD and/or source/drain implant steps to enhance circuit performance | Mark I. Gardner, H. Jim Fulford | 1998-08-11 |
| 5792706 | Interlevel dielectric with air gaps to reduce permitivity | Mark W. Michael, Robert Dawson, Basab Bandyopadhyay, H. Jim Fulford, William S. Brennan | 1998-08-11 |
| 5789298 | High performance mosfet structure having asymmetrical spacer formation and method of making the same | Mark I. Gardner | 1998-08-04 |
| 5786256 | Method of reducing MOS transistor gate beyond photolithographically patterned dimension | Mark I. Gardner, H. Jim Fulford | 1998-07-28 |
| 5783458 | Asymmetrical p-channel transistor having nitrided oxide patterned to allow select formation of a grown sidewall spacer | Daniel Kadosh, Robert Dawson | 1998-07-21 |