Issued Patents All Time
Showing 76–100 of 141 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 5937310 | Reduced bird's beak field oxidation process using nitrogen implanted into active region | Mark I. Gardner, Kuang-Yeh Chang | 1999-08-10 |
| 5926693 | Two level transistor formation for optimum silicon utilization | Mark I. Gardner, Jon D. Cheek | 1999-07-20 |
| 5926717 | Method of making an integrated circuit with oxidizable trench liner | Mark W. Michael, Robert Dawson, Basab Bandyopadhyay, H. Jim Fulford, William S. Brennan | 1999-07-20 |
| 5926713 | Method for achieving global planarization by forming minimum mesas in large field areas | Basab Bandyopadhyay, H. Jim Fulford, Robert Dawson, Mark W. Michael, William S. Brennan | 1999-07-20 |
| 5924008 | Integrated circuit having local interconnect for reducing signal cross coupled noise | Mark W. Michael, Robert Dawson, Basab Bandyopadhyay, H. Jim Fulford, William S. Brennan | 1999-07-13 |
| 5923992 | Integrated circuit formed with shallow isolation structures having nitride placed on the trench dielectric | Thomas E. Spikes, Jr., Mark I. Gardner | 1999-07-13 |
| 5918134 | Method of reducing transistor channel length with oxidation inhibiting spacers | Mark I. Gardner, H. Jim Fulford | 1999-06-29 |
| 5918130 | Transistor fabrication employing formation of silicide across source and drain regions prior to formation of the gate conductor | Mark I. Gardner, H. Jim Fulford | 1999-06-29 |
| 5916715 | Process of using electrical signals for determining lithographic misalignment of vias relative to electrically active elements | H. Jim Fulford, Mark I. Gardner | 1999-06-29 |
| 5912493 | Enhanced oxidation for spacer formation integrated with LDD implantation | Mark I. Gardner, Charles E. May | 1999-06-15 |
| 5908315 | Method for forming a test structure to determine the effect of LDD length upon transistor performance | Mark I. Gardner, H. Jim Fulford | 1999-06-01 |
| 5907764 | In-line detection and assessment of net charge in PECVD silicon dioxide (oxide) layers | John K. Lowell, Robert Dawson | 1999-05-25 |
| 5905285 | Ultra short trench transistors and process for making same | Mark I. Gardner | 1999-05-18 |
| 5904539 | Semiconductor trench isolation process resulting in a silicon mesa having enhanced mechanical and electrical properties | Robert Dawson, Charles E. May, Mark I. Gardner, Kuang-Yeh Chang | 1999-05-18 |
| 5899727 | Method of making a semiconductor isolation region bounded by a trench and covered with an oxide to improve planarization | Basab Bandyopadhyay, H. Jim Fulford, Robert Dawson, Mark W. Michael, William S. Brennan | 1999-05-04 |
| 5895955 | MOS transistor employing a removable, dual layer etch stop to protect implant regions from sidewall spacer overetch | Mark I. Gardner, H. Jim Fulford | 1999-04-20 |
| 5894168 | Mask generation technique for producing an integrated circuit with optimal polysilicon interconnect layout for achieving global planarization | Mark W. Michael, Robert Dawson, Basab Bandyopadhyay, H. Jim Fulford, William S. Brennan | 1999-04-13 |
| 5893750 | Method for forming a highly planarized interlevel dielectric structure | — | 1999-04-13 |
| 5893739 | Asymmetrical P-channel transistor having a boron migration barrier and a selectively formed sidewall spacer | Daniel Kadosh, Jon D. Cheek | 1999-04-13 |
| 5891793 | Transistor fabrication process employing a common chamber for gate oxide and gate conductor formation | Mark I. Gardner | 1999-04-06 |
| 5885879 | Thin polysilicon masking technique for improved lithography control | Mark I. Gardner | 1999-03-23 |
| 5882993 | Integrated circuit with differing gate oxide thickness and process for making same | Mark I. Gardner | 1999-03-16 |
| 5882973 | Method for forming an integrated circuit having transistors of dissimilarly graded junction profiles | Mark I. Gardner, H. Jim. Fulford, Jr. | 1999-03-16 |
| 5861335 | Semiconductor fabrication employing a post-implant anneal within a low temperature high pressure nitrogen ambient to improve channel and gate oxide reliability | Mark I. Gardner | 1999-01-19 |
| 5854515 | Integrated circuit having conductors of enhanced cross-sectional area | Basab Bandyopadhyay, H. Jim Fulford, Robert Dawson, Mark W. Michael, William S. Brennan | 1998-12-29 |