Issued Patents All Time
Showing 126–141 of 141 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 5783864 | Multilevel interconnect structure of an integrated circuit having air gaps and pillars separating levels of interconnect | Robert Dawson, Mark W. Michael, William S. Brennan, Basab Bandyopadhyay, H. Jim Fulford | 1998-07-21 |
| 5783481 | Semiconductor interlevel dielectric having a polymide for producing air gaps | William S. Brennan, Robert Dawson, H. Jim Fulford, Basab Bandyopadhyay, Mark W. Michael | 1998-07-21 |
| 5770483 | Multi-level transistor fabrication method with high performance drain-to-gate connection | Daniel Kadosh, Mark I. Gardner | 1998-06-23 |
| 5770517 | Semiconductor fabrication employing copper plug formation within a contact area | Mark I. Gardner | 1998-06-23 |
| 5766803 | Mask generation technique for producing an integrated circuit with optimal metal interconnect layout for achieving global planarization | Mark W. Michael, Robert Dawson, Basab Bandyopadhyay, H. Jim Fulford, William S. Brennan | 1998-06-16 |
| 5767012 | Method of forming a recessed interconnect structure | H. Jim Fulford, Basab Bandyopadhyay, Robert Dawson, Mark W. Michael, William S. Brennan | 1998-06-16 |
| 5767000 | Method of manufacturing subfield conductive layer | H. Jim Fulford, Robert Dawson, Basab Bandyopadhyay, Mark W. Michael, William S. Brennan | 1998-06-16 |
| 5763311 | High performance asymmetrical MOSFET structure and method of making the same | Mark I. Gardner, Daniel Kadosh | 1998-06-09 |
| 5759913 | Method of formation of an air gap within a semiconductor dielectric by solvent desorption | H. Jim Fulford, Robert Dawson, Basab Bandyopadhyay, Mark W. Michael, William S. Brennan | 1998-06-02 |
| 5747852 | LDD MOS transistor with improved uniformity and controllability of alignment | K.T Chang, Mark I. Gardner | 1998-05-05 |
| 5733798 | Mask generation technique for producing an integrated circuit with optimal polysilicon interconnect layout for achieving global planarization | Mark W. Michael, Robert Dawson, Basab Bandyopadhyay, H. Jim Fulford, William S. Brennan | 1998-03-31 |
| 5719067 | Trench transistor and method for making same | Mark I. Gardner | 1998-02-17 |
| 5717242 | Integrated circuit having local interconnect for reduing signal cross coupled noise | Mark W. Michael, Robert Dawson, Basab Bandyopadhyay, H. Jim Fulford, William S. Brennan | 1998-02-10 |
| 5679585 | Method for forming metal silicide on a semiconductor surface with minimal effect on pre-existing implants | Mark I. Gardner, Derick J. Wristers, Dim-Lee Kwong | 1997-10-21 |
| 5679605 | Multilevel interconnect structure of an integrated circuit formed by a single via etch and dual fill process | William S. Brennan, Robert Dawson, H. Jim Fulford, Basab Bandyopadhyay, Mark W. Michael | 1997-10-21 |
| 5643825 | Integrated circuit isolation process | Mark I. Gardner, Kuang-Yeh Chang | 1997-07-01 |