Issued Patents All Time
Showing 26–50 of 141 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6159814 | Spacer formation by poly stack dopant profile design | Mark I. Gardner, Charles E. May | 2000-12-12 |
| 6156649 | Method of forming uniform sheet resistivity salicide | Robert Dawson, Charles E. May | 2000-12-05 |
| 6153833 | Integrated circuit having interconnect lines separated by a dielectric having a capping layer | Robert Dawson, Mark W. Michael, Basab Bandyopadhyay, H. Jim Fulford, William S. Brennan | 2000-11-28 |
| 6150721 | Integrated circuit which uses a damascene process for producing staggered interconnect lines | Basab Bandyopadhyay, H. Jim Fulford, Robert Dawson, Mark W. Michael, William S. Brennan | 2000-11-21 |
| 6137182 | Method of reducing via and contact dimensions beyond photolithography equipment limits | Mark I. Gardner, Robert Dawson | 2000-10-24 |
| 6127264 | Integrated circuit having conductors of enhanced cross-sectional area | Basab Bandyopadhyay, H. Jim Fulford, Robert Dawson, Mark W. Michael, William S. Brennan | 2000-10-03 |
| 6127719 | Subfield conductive layer and method of manufacture | H. Jim Fulford, Robert Dawson, Basab Bandyopadhyay, Mark W. Michael, William S. Brennan | 2000-10-03 |
| 6121631 | Test structure to determine the effect of LDD length upon transistor performance | Mark I. Gardner, H. Jim Fulford | 2000-09-19 |
| 6121138 | Collimated deposition of titanium onto a substantially vertical nitride spacer sidewall to prevent silicide bridging | Karsten Wieczorek | 2000-09-19 |
| 6117760 | Method of making a high density interconnect formation | Mark I. Gardner, H. Jim Fulford | 2000-09-12 |
| 6117742 | Method for making a high performance transistor | Mark I. Gardner | 2000-09-12 |
| 6117739 | Semiconductor device with layered doped regions and methods of manufacture | Mark I. Gardner, Charles E. May | 2000-09-12 |
| 6118137 | Test structure responsive to electrical signals for determining lithographic misalignment of conductors relative to vias | H. Jim Fulford, Mark I. Gardner | 2000-09-12 |
| 6107129 | Integrated circuit having multiple LDD and/or source/drain implant steps to enhance circuit performance | Mark I. Gardner, H. Jim Fulford | 2000-08-22 |
| 6104064 | Asymmetrical transistor structure | Daniel Kadosh, Mark I. Gardner, Michael Duane, Jon D. Cheek, Robert Dawson +1 more | 2000-08-15 |
| 6097096 | Metal attachment method and structure for attaching substrates at low temperatures | Mark I. Gardner, Daniel Kadosh | 2000-08-01 |
| 6091149 | Dissolvable dielectric method and structure | Basab Bandyopadhyay, Robert Dawson, H. Jim Fulford, Mark W. Michael, William S. Brennan | 2000-07-18 |
| 6090703 | Method of forming an integrated circuit having conductors of enhanced cross-sectional area with etch stop barrier layer | Basab Bandyopadhyay, H. Jim Fulford, William S. Brennan, Robert Dawson, Mark W. Michael | 2000-07-18 |
| 6090694 | Local interconnect patterning and contact formation | Charles E. May, Mark I. Gardner | 2000-07-18 |
| 6087249 | Transistor fabrication process employing a common chamber for gate oxide and gate conductor formation | Mark I. Gardner | 2000-07-11 |
| 6083846 | Graded MOS transistor junction formed by aligning a sequence of implants to a selectively removable polysilicon sidewall space and oxide thermally grown thereon | H. Jim Fulford, Mark I. Gardner | 2000-07-04 |
| 6080640 | Metal attachment method and structure for attaching substrates at low temperatures | Mark I. Gardner, Daniel Kadosh | 2000-06-27 |
| 6072192 | Test structure responsive to electrical signals for determining lithographic misalignment of vias relative to electrically active elements | H. Jim Fulford, Mark I. Gardner | 2000-06-06 |
| 6063679 | Spacer formation for graded dopant profile having a triangular geometry | Mark I. Gardner, Charles E. May | 2000-05-16 |
| 6054385 | Elevated local interconnect and contact structure | Mark I. Gardner | 2000-04-25 |