Issued Patents All Time
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6140216 | Post etch silicide formation using dielectric etchback after global planarization | Shyam Garg | 2000-10-31 |
| 5774395 | Electrically erasable reference cell for accurately determining threshold voltage of a non-volatile memory at a plurality of threshold voltage levels | Shyam Garg | 1998-06-30 |
| 5717632 | Apparatus and method for multiple-level storage in non-volatile memories | Shyam Garg | 1998-02-10 |
| 5581502 | Method for reading a non-volatile memory array | Nipendra J. Patel, Shyam Garg | 1996-12-03 |
| 5546340 | Non-volatile memory array with over-erase correction | Chung-You Hu, Shyam Garg, Sanjay Banerjee | 1996-08-13 |
| 5427963 | Method of making a MOS device with drain side channel implant | Shyam Garg, Bradley T. Moore | 1995-06-27 |
| 5376573 | Method of making a flash EPROM device utilizing a single masking step for etching and implanting source regions within the EPROM core and redundancy areas | Shyam Garg, Fei Wang | 1994-12-27 |