Issued Patents All Time
Showing 1–11 of 11 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6438030 | Non-volatile memory, method of manufacture, and method of programming | Kuo-Tung Chang, Wei Liu, David Burnett | 2002-08-20 |
| 6266275 | Dual source side polysilicon select gate structure and programming method utilizing single tunnel oxide for nand array flash memory | Paul L. Chen, Mike Van Buskirk, Shane Hollmer, Binh Quang Le, Shoichi Kawamura +3 more | 2001-07-24 |
| 6009014 | Erase verify scheme for NAND flash | Shane Hollmer, Binh Quang Le, Pau-Ling Chen, Jonathan S. Su, Ravi Prakash Gutala +1 more | 1999-12-28 |
| 5999452 | Dual source side polysilicon select gate structure and programming method utilizing single tunnel oxide for NAND array flash memory | Pau-Ling Chen, Mike Van Buskirk, Shane Hollmer, Binh Quang Le, Shoichi Kawamura +3 more | 1999-12-07 |
| 5912489 | Dual source side polysilicon select gate structure utilizing single tunnel oxide for NAND array flash memory | Pau-Ling Chen, Mike Van Buskirk, Shane Hollmer, Binh Quang Le, Shoichi Kawamura +3 more | 1999-06-15 |
| 5909396 | High voltage NMOS pass gate having supply range, area, and speed advantages | Binh Quang Le, Pau-Ling Chen, Shane Hollmer, Narbeh Derhacobian | 1999-06-01 |
| 5861338 | Channel stop implant profile shaping scheme for field isolation | — | 1999-01-19 |
| 5844840 | High voltage NMOS pass gate having supply range, area, and speed advantages | Binh Quang Le, Pau-Ling Chen, Shane Hollmer, Narbeh Derhacobian | 1998-12-01 |
| 5793677 | Using floating gate devices as select gate devices for NAND flash memory and its bias scheme | Yu Sun, Chi Chang, Sameer Haddad | 1998-08-11 |
| 5715194 | Bias scheme of program inhibit for random programming in a nand flash memory | — | 1998-02-03 |
| 5546340 | Non-volatile memory array with over-erase correction | Robert B. Richart, Shyam Garg, Sanjay Banerjee | 1996-08-13 |