Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
ND

Narbeh Derhacobian — 57 Patents

AMD: 39 patents #218 of 9,280Top 3%
ATAdesto Technologies: 12 patents #12 of 52Top 25%
Fujitsu Limited: 6 patents #5,180 of 24,456Top 25%
ALAgate Logic: 2 patents #18 of 48Top 40%
VLVirage Logic: 2 patents #29 of 67Top 45%
ATAdesto Technology: 1 patents #4 of 8Top 50%
Belmont, CA: #23 of 1,494 inventorsTop 2%
California: #6,412 of 386,348 inventorsTop 2%
Overall (All Time): #42,642 of 4,157,543Top 2%
57 Patents All Time
Narbeh Derhacobian has been granted 57 US patents while listed as an inventor at AMD. The first was granted in 1998 and the most recent in October 2019. Narbeh Derhacobian ranks #42,642 of 4,157,543 US inventors in our database (top 1.0%). Patent records list Narbeh Derhacobian in Belmont, CA, US.

Patents per Year

Patents granted per year, 1998 to 2019Bar chart with a peak of 12 patents in 2002.peak 121998: 1 patents19981999: 2 patents2000: 4 patents20002001: 10 patents2002: 12 patents20022003: 9 patents2004: 2 patents20042006: 1 patents2010: 1 patents20102012: 4 patents2014: 5 patents20142015: 4 patents2017: 1 patents20172019: 1 patents2019

Issued Patents All Time

Showing 1–25 of 57 patents

Patent #TitleCo-InventorsDateApprox Value ⓘ
10446747 Methods of operating integrated circuit devices having volatile and nonvolatile memory portions Shane Hollmer 2019-10-15
9570166 Read operations and circuits for memory devices having programmable elements, including programmable resistance elements Nad Edward Gilbert, Ishai Naveh 2017-02-14 $1,346,000
9159414 Programmable impedance element circuits and methods Shane Hollmer, John Dinh 2015-10-13
9007814 Application of relaxation voltage pulses to programmble impedance elements during read operations 2015-04-14
8995173 Memory cells, devices and method with dynamic storage elements and programmable impedance shadow elements 2015-03-31
8947913 Circuits and methods having programmable impedance elements Ishai Naveh 2015-02-03
8913444 Read operations and circuits for memory devices having programmable elements, including programmable resistance elements Nad Edward Gilbert, Ishai Naveh 2014-12-16
8822967 Multi-terminal phase change devices Louis Charles Kordus, II, Antonietta Oliva, Vei-Han Chan 2014-09-02
8687403 Circuits having programmable impedance elements Shane Hollmer, Ishai Naveh 2014-04-01
8675396 Integrated circuit devices and systems having programmable impedance elements with different response types Ishai Naveh, Shane Hollmer 2014-03-18
8659926 PMC-based non-volatile CAM 2014-02-25
8331128 Reconfigurable memory arrays having programmable impedance elements and corresponding methods Shane Hollmer 2012-12-11
8320148 PMC-based non-volatile CAM 2012-11-27
8294488 Programmable impedance element circuits and methods Shane Hollmer, John Dinh 2012-10-23
8183551 Multi-terminal phase change devices Louis Charles Kordus, II, Antonietta Oliva, Vei-Han Chan 2012-05-22
7755389 Reconfigurable logic structures Colin N. Murphy, Louis Charles Kordus, II, Antonietta Oliva, Vei-Han Chan, Thomas E. Stewart 2010-07-13
7095076 Electrically-alterable non-volatile memory cell Kim Han, Jaroslav Raszka 2006-08-22 $1,651,000
6788574 Electrically-alterable non-volatile memory cell Kim Han, Jaroslav Raszka 2004-09-07 $2,544,000
6750157 Nonvolatile memory cell with a nitridated oxide layer Richard Fastow, Chi Chang 2004-06-15 $4,556,000
6618290 Method of programming a non-volatile memory cell using a baking process Janet Wang 2003-09-09 $4,832,000
6590811 Higher program VT and faster programming rates based on improved erase methods Darlene Hamilton, Janet Wang, Kulachet Tanpairoj 2003-07-08 $2,679,000
6567303 Charge injection Darlene Hamilton, Janet Wang, Tim Thurgate, Michael Han 2003-05-20 $2,116,000
6555436 Simultaneous formation of charge storage and bitline to wordline isolation Mark T. Ramsbey, Jean Y. Yang, Hidehiko Shiraiwa, Michael A. Van Buskirk, David Michael Rogers +3 more 2003-04-29 $1,822,000
6549466 Using a negative gate erase voltage applied in steps of decreasing amounts to reduce erase time for a non-volatile memory cell with an oxide-nitride-oxide (ONO) structure Michael A. Van Buskirk, Chi Chang, Daniel Sobek 2003-04-15 $2,272,000
6541816 Planar structure for non-volatile memory devices Mark T. Ramsbey, Jean Y. Yang, Hidehiko Shiraiwa, Michael A. Van Buskirk, David Michael Rogers +2 more 2003-04-01 $3,014,000