Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Using a negative gate erase voltage applied in steps of decreasing amounts to reduce erase time for a non-volatile memory cell with an oxide-nitride-oxide (ONO) structure

Using a negative gate erase voltage applied in steps of decreasing amounts to reduce erase time for a non-volatile memory cell with an oxide-nitride-oxide (ONO) structure

US Patent 6549466 · Granted Apr 15, 2003

Estimated economic value: $2,272,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Time-of-flight optical measurement and decoding of fast-optical signals2024
Non-invasive system and method for product formulation assessment based on produ2024
Boron-containing porous membranes and methods of use thereof2023
Method of using oxygenated metal compounds for selective extraction of lithium s2023
Alkaline anion exchange membranes and methods of use thereof2023
Non-invasive systems and methods for detecting mental impairment2023
Tetravalent boron-containing proton-exchange solid supports and methods of makin2023
Time-of-flight optical measurement and decoding of fast-optical signals2022
Methods and systems using molecular glue for covalent bonding of solid substrate2022
Wafer storage device, carrier plate and wafer cassette2022
Integrated magnetometer arrays for magnetoencephalography (MEG) detection system2022
Boron-containing porous membranes and methods of use thereof2022