Issued Patents All Time
Showing 26–50 of 57 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6529410 | NAND array structure and method with buried layer | Michael Han | 2003-03-04 |
| 6519182 | Using hot carrier injection to control over-programming in a non-volatile memory cell having an oxide-nitride-oxide (ONO) structure | Daniel Sobek | 2003-02-11 |
| 6514830 | Method of manufacturing high voltage transistor with modified field implant mask | Hao Fang | 2003-02-04 |
| 6501681 | Using a low drain bias during erase verify to ensure complete removal of residual charge in the nitride in sonos non-volatile memories | Michael A. Van Buskirk | 2002-12-31 |
| 6493261 | Single bit array edges | Darlene Hamilton, Kulachet Tanpairoj, Ravi Sunkavalli, Michael A. Van Buskirk | 2002-12-10 |
| 6468865 | Method of simultaneous formation of bitline isolation and periphery oxide | Jean Y. Yang, Mark T. Ramsbey, Hidehiko Shiraiwa, Michael A. Van Buskirk, David Michael Rogers +3 more | 2002-10-22 |
| 6465303 | Method of manufacturing spacer etch mask for silicon-oxide-nitride-oxide-silicon (SONOS) type nonvolatile memory | Mark T. Ramsbey, Janet Wang, Angela T. Hui, Tuan Pham, Ravi Sunkavalli +1 more | 2002-10-15 |
| 6465306 | Simultaneous formation of charge storage and bitline to wordline isolation | Mark T. Ramsbey, Jean Y. Yang, Hidehiko Shiraiwa, Michael A. Van Buskirk, David Michael Rogers +3 more | 2002-10-15 |
| 6456533 | Higher program VT and faster programming rates based on improved erase methods | Darlene Hamilton, Janet Wang, Kulachet Tanpairoj | 2002-09-24 |
| 6456536 | Method of programming a non-volatile memory cell using a substrate bias | Daniel Sobek, Timothy Thurgate, Janet Wang | 2002-09-24 |
| 6442074 | Tailored erase method using higher program VT and higher negative gate erase | Darlene Hamilton, Kulachet Tanpairoj, Ravi Sunkavalli | 2002-08-27 |
| 6381179 | Using a negative gate erase to increase the cycling endurance of a non-volatile memory cell with an oxide-nitride-oxide (ONO) structure | Michael Van Buskirk, Chi Chang, Daniel Sobek | 2002-04-30 |
| 6369433 | High voltage transistor with low body effect and low leakage | Pau-Ling Chen, Hao Fang | 2002-04-09 |
| 6356482 | Using negative gate erase voltage to simultaneously erase two bits from a non-volatile memory cell with an oxide-nitride-oxide (ONO) gate structure | Michael Van Buskirk, Chi Chang, Daniel Sobek | 2002-03-12 |
| 6351017 | High voltage transistor with modified field implant mask | Hao Fang | 2002-02-26 |
| 6331953 | Intelligent ramped gate and ramped drain erasure for non-volatile memory cells | Janet Wang, Daniel Sobek | 2001-12-18 |
| 6331952 | Positive gate erasure for non-volatile memory cells | Janet Wang, Ravi Sunkavalli | 2001-12-18 |
| 6327183 | Nonlinear stepped programming voltage | Joseph G. Pawletko, K. Michael Han | 2001-12-04 |
| 6307784 | Negative gate erase | Darlene Hamilton, Kulachet Tanpairoj, Ravi Sunkavalli | 2001-10-23 |
| 6269023 | Method of programming a non-volatile memory cell using a current limiter | Janet Wang, Daniel Sobek, Sameer Haddad | 2001-07-31 |
| 6246610 | Symmetrical program and erase scheme to improve erase time degradation in NAND devices | K. Michael Han, Joseph G. Pawletko, Chi Chang | 2001-06-12 |
| 6228782 | Core field isolation for a NAND flash memory | Hao Fang, Massaki Higashitani | 2001-05-08 |
| 6215702 | Method of maintaining constant erasing speeds for non-volatile memory cells | Shane Hollmer, Ravi Sunkavalli | 2001-04-10 |
| 6188606 | Multi state sensing of NAND memory cells by varying source bias | Hao Fang, Michael Han | 2001-02-13 |
| 6177322 | High voltage transistor with high gated diode breakdown voltage | Pau-Ling Chen, Hao Fang, Timothy Thurgate | 2001-01-23 |