Issued Patents All Time
Showing 51–75 of 100 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6444539 | Method for producing a shallow trench isolation filled with thermal oxide | Angela T. Hui, Yue-Song He, Tatsuya Kajita, Mark S. Chang, Chi Chang +1 more | 2002-09-03 |
| 6444530 | Process for fabricating an integrated circuit with a self-aligned contact | Hung-Sheng Chen, Unsoon Kim, Chi Chang, Mark T. Ramsbey, Mark Randolph +4 more | 2002-09-03 |
| 6440797 | Nitride barrier layer for protection of ONO structure from top oxide loss in a fabrication of SONOS flash memory | Yider Wu, Jean Y. Yang, Mark T. Ramsbey, Emmanuel H. Lingunis | 2002-08-27 |
| 6429108 | Non-volatile memory device with encapsulated tungsten gate and method of making same | Chi Chang, Richard J. Huang, Keizaburo Yoshie | 2002-08-06 |
| 6420752 | Semiconductor device with self-aligned contacts using a liner oxide layer | Minh Van Ngo, Fei Wang, Mark T. Ramsbey, Chi Chang, Angela T. Hui +1 more | 2002-07-16 |
| 6403420 | Nitrogen implant after bit-line formation for ONO flash memory devices | Jean Y. Yang, Yider Wu, Mark T. Ramsbey | 2002-06-11 |
| 6399984 | Species implantation for minimizing interface defect density in flash memory devices | Yider Wu, Mark T. Ramsbey, Chi Chang, Tuan Pham, Jean Y. Yang | 2002-06-04 |
| 6369416 | Semiconductor device with contacts having a sloped profile | Angela T. Hui, Tuan Pham, Mark T. Ramsbey | 2002-04-09 |
| 6359307 | Method for forming self-aligned contacts and interconnection lines using dual damascene techniques | Fei Wang, Hiroyuki Kinoshita, Kashmir Sahota, Wenge Yang | 2002-03-19 |
| 6348379 | Method of forming self-aligned contacts using consumable spacers | Fei Wang, Ramkumar Subramanian | 2002-02-19 |
| 6346467 | Method of making tungsten gate MOS transistor and memory cell by encapsulating | Chi Chang, Richard J. Huang, Keizaburo Yoshie | 2002-02-12 |
| 6342415 | Method and system for providing reduced-sized contacts in a semiconductor device | Angela T. Hui, Tuan Pham, Mark T. Ramsbey | 2002-01-29 |
| 6306713 | Method for forming self-aligned contacts and local interconnects for salicided gates using a secondary spacer | YongZhong Hu, Fei Wang, Wenge Yang, Hiroyuki Kinoshita | 2001-10-23 |
| 6284600 | Species implantation for minimizing interface defect density in flash memory devices | Yider Wu, Mark T. Ramsbey, Chi Chang, Tuan Pham, Jean Y. Yang | 2001-09-04 |
| 6274433 | Methods and arrangements for forming a floating gate in non-volatile memory semiconductor devices | Mark T. Ramsbey, Tuan Pham, Kenneth Wo-Wai Au | 2001-08-14 |
| 6271087 | Method for forming self-aligned contacts and local interconnects using self-aligned local interconnects | Hiroyuki Kinoshita, YongZhong Hu, Fei Wang | 2001-08-07 |
| 6266275 | Dual source side polysilicon select gate structure and programming method utilizing single tunnel oxide for nand array flash memory | Paul L. Chen, Mike Van Buskirk, Shane Hollmer, Binh Quang Le, Shoichi Kawamura +3 more | 2001-07-24 |
| 6252276 | Non-volatile semiconductor memory device including assymetrically nitrogen doped gate oxide | Mark T. Ramsbey, Sameer Haddad, Vei-Han Chan, Chi Chang | 2001-06-26 |
| 6248627 | Method for protecting gate edges from charge gain/loss in semiconductor device | Tuan Pham, Mark T. Ramsbey, Sameer Haddad, Angela T. Hui, Chi Chang | 2001-06-19 |
| 6235587 | Method of manufacturing a semiconductor device with reduced arc loss in peripheral circuitry region | Tommy C. Hsaio, Mark T. Ramsbey | 2001-05-22 |
| 6235584 | Method and system for reducing short channel effects in a memory device | Mark T. Ramsbey, Tommy Hsiao | 2001-05-22 |
| 6232630 | Light floating gate doping to improve tunnel oxide reliability | Mark T. Ramsbey, Tuan Pham, Kenneth Wo-Wai Au, David Chi | 2001-05-15 |
| 6232646 | Shallow trench isolation filled with thermal oxide | Angela T. Hui, Yue-Song He, Tatsuya Kajita, Mark S. Chang, Chi Chang +1 more | 2001-05-15 |
| 6200857 | Method of manufacturing a semiconductor device without arc loss in peripheral circuit region | Tommy Hsiao, Mark T. Ramsbey | 2001-03-13 |
| 6197635 | Method of manufacturing a semiconductor device with reduced masking and without ARC loss in peripheral circuitry region | Tommy C. Hsaio, Mark T. Ramsbey | 2001-03-06 |