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Self aligned memory element and wordline |
Patrick K. Cheung |
2010-01-12 |
| 7220985 |
Self aligned memory element and wordline |
Patrick K. Cheung |
2007-05-22 |
| 7005386 |
Method for reducing resist height erosion in a gate etch process |
Scott A. Bell, Srikanteswara Dakshina-Murthy, Chih-Yuh Yang |
2006-02-28 |
| 6962849 |
Hard mask spacer for sublithographic bitline |
Tazrien Kamal, Weidong Qian, Kouros Ghandehari, Taraneh Jamali-Beh, Mark T. Ramsbey |
2005-11-08 |
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System and method of forming a passive layer by a CMP process |
Ramkumar Subramanian, Jane V. Oglesby, Minh Van Ngo, Mark S. Chang, Sergey Lopatin +3 more |
2004-12-28 |
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Enhanced transistor gate using E-beam radiation |
Philip A. Fisher, Chih-Yuh Yang, Marina V. Plat, Russell R.A. Callahan |
2004-12-07 |
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Silicon containing material for patterning polymeric memory element |
Ramkumar Subramanian, Christopher F. Lyons, Matthew S. Buynoski, Patrick K. Cheung, Angela T. Hui +5 more |
2004-10-12 |
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Polymer memory device formed in via opening |
Nicholas H. Tripsas, Matthew S. Buynoski, Suzette K. Pangrle, Uzodinma Okoroanyanwu, Angela T. Hui +7 more |
2004-09-07 |
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Method of achieving stable deep ultraviolet (DUV) resist etch rate for gate critical dimension (CD) |
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2002-09-24 |