Issued Patents All Time
Showing 1–24 of 24 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11506338 | Internal casing for pressurized fluid storage tank for a motor vehicle | Bjorn Criel, Pierre De Keyzer | 2022-11-22 |
| 10707119 | Interconnect structures with airgaps and dielectric-capped interconnects | Nicholas V. LiCausi, Vimal Kamineni | 2020-07-07 |
| 10395981 | Semiconductor device including a leveling dielectric fill material | Hans-Peter Moll | 2019-08-27 |
| 10049944 | Method of manufacturing selective nanostructures into finFET process flow | Scott Beasor | 2018-08-14 |
| 9875936 | Spacer defined fin growth and differential fin width | Ryan Sporer, Rohit Pal | 2018-01-23 |
| 9660075 | Integrated circuits with dual silicide contacts and methods for fabricating same | Shao-Ming Koh, Guillaume Bouche, Andy Wei | 2017-05-23 |
| 9634143 | Methods of forming FinFET devices with substantially undoped channel regions | Ryan Sporer | 2017-04-25 |
| 9570344 | Method to protect MOL metallization from hardmask strip process | Vimal Kamineni, Nicholas V. LiCausi, Shariq Siddiqui | 2017-02-14 |
| 9508712 | Semiconductor device with a multiple nanowire channel structure and methods of variably connecting such nanowires for current density modulation | Nicholas V. LiCausi | 2016-11-29 |
| 9293462 | Integrated circuits with dual silicide contacts and methods for fabricating same | Shao-Ming Koh, Guillaume Bouche, Andy Wei | 2016-03-22 |
| 9196694 | Integrated circuits with dual silicide contacts and methods for fabricating same | Guillaume Bouche, Shao-Ming Koh, Andy Wei | 2015-11-24 |
| 9177805 | Integrated circuits with metal-insulator-semiconductor (MIS) contact structures and methods for fabricating same | Guillaume Bouche, Shao-Ming Koh, Andy Wei | 2015-11-03 |
| 8969207 | Methods of forming a masking layer for patterning underlying structures | Gerard Schmid, Richard A. Farrell, Chanro Park | 2015-03-03 |
| 8963255 | Strained silicon carbide channel for electron mobility of NMOS | Kingsuk Maitra | 2015-02-24 |
| 8906802 | Methods of forming trench/via features in an underlying structure using a process that includes a masking layer formed by a directed self-assembly process | Gerard Schmid, Richard A. Farrell, Chanro Park | 2014-12-09 |
| 8853019 | Methods of forming a semiconductor device with a nanowire channel structure by performing an anneal process | Jody A. Fronheiser, Kerem Akarvardar, Ajey Poovannummoottil Jacob, Daniel T. Pham | 2014-10-07 |
| 8846511 | Methods of trimming nanowire structures | Nicholas V. LiCausi | 2014-09-30 |
| 8759904 | Electronic device having plural FIN-FETs with different FIN heights and planar FETs on the same substrate | Kingsuk Maitra | 2014-06-24 |
| 8722482 | Strained silicon carbide channel for electron mobility of NMOS | Kingsuk Maitra | 2014-05-13 |
| 8691640 | Methods of forming dielectrically isolated fins for a FinFET semiconductor by performing an etching process wherein the etch rate is modified via inclusion of a dopant material | Nicholas V. LiCausi | 2014-04-08 |
| 8481410 | Methods of epitaxial FinFET | Nicholas V. LiCausi | 2013-07-09 |
| 8476137 | Methods of FinFET height control | Nicholas V. LiCausi | 2013-07-02 |
| 8460984 | FIN-FET device and method and integrated circuits using such | Kingsuk Maitra | 2013-06-11 |
| 7998846 | 3-D integrated circuit system and method | Eunha Kim, Shenqing Fang, Youseok Suh, Kuo-Tung Chang, Yi Ma +2 more | 2011-08-16 |