Issued Patents All Time
Showing 26–50 of 68 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6933219 | Tightly spaced gate formation through damascene process | Emmanuil H. Lingunis, Krishnashree Achuthan, Minh Van Ngo, Cyrus E. Tabery | 2005-08-23 |
| 6927145 | Bitline hard mask spacer flow for memory cell scaling | Mark T. Ramsbey, Jaeyong Park, Tazrien Kamal, Emmanuil H. Lingunis | 2005-08-09 |
| 6897533 | Multi-bit silicon nitride charge-trapping non-volatile memory cell | Yider Wu | 2005-05-24 |
| 6884681 | Method of manufacturing a semiconductor memory with deuterated materials | Tazrien Kamal, Arvind Halliyal, Minh Van Ngo, Mark T. Ramsbey, Hidehiko Shiraiwa +1 more | 2005-04-26 |
| 6869844 | Method and structure for protecting NROM devices from induced charge damage during device fabrication | Zhizheng Liu, Yider Wu | 2005-03-22 |
| 6855608 | Method of fabricating a planar structure charge trapping memory cell array with rectangular gates and reduced bit line resistance | Mark T. Ramsbey, Mark Randolph, Hiroyuki Kinoshita, Cyrus E. Tabery, Jeff P. Erhardt +3 more | 2005-02-15 |
| 6803275 | ONO fabrication process for reducing oxygen vacancy content in bottom oxide layer in flash memory devices | Jaeyong Park, Hidehiko Shiraiwa, Arvind Halliyal, Inkuk Kang, Tazrien Kamal +1 more | 2004-10-12 |
| 6797565 | Methods for fabricating and planarizing dual poly scalable SONOS flash memory | Yider Wu, Zhizheng Liu | 2004-09-28 |
| 6767791 | Structure and method for suppressing oxide encroachment in a floating gate memory cell | Yider Wu, Harpreet Sachar | 2004-07-27 |
| 6765254 | Structure and method for preventing UV radiation damage and increasing data retention in memory cells | Angela T. Hui, Minh Van Ngo, Ning Cheng, Jaeyong Park, Hidehiko Shiraiwa +3 more | 2004-07-20 |
| 6754106 | Reference cell with various load circuits compensating for source side loading effects in a non-volatile memory | Yider Wu, Jiang Li | 2004-06-22 |
| 6744105 | Memory array having shallow bit line with silicide contact portion and method of formation | Cinti X. Chen, Hiroyuki Kinoshita, Jeff P. Erhardt, Weidong Qian | 2004-06-01 |
| 6737701 | Structure and method for reducing charge loss in a memory cell | Amy C. Tu, Yider Wu | 2004-05-18 |
| 6720133 | Memory manufacturing process using disposable ARC for wordline formation | Mark T. Ramsbey, Kouros Ghandehari, Tazrien Kamal, Emmanuil H. Lingunis, Hidehiko Shiraiwa | 2004-04-13 |
| 6707078 | Dummy wordline for erase and bitline leakage | Hidehiko Shiraiwa, Yider Wu, Mark T. Ramsbey, Darlene Hamilton | 2004-03-16 |
| 6706595 | Hard mask process for memory device without bitline shorts | Mark T. Ramsbey, Hidehiko Shiraiwa, Yider Wu, Emmanuil Lingunis, Tazrien Kamal | 2004-03-16 |
| 6680509 | Nitride barrier layer for protection of ONO structure from top oxide loss in fabrication of SONOS flash memory | Yider Wu, Mark T. Ramsbey, Emmanuel H. Lingunis, Yu Sun | 2004-01-20 |
| 6670241 | Semiconductor memory with deuterated materials | Tazrien Kamal, Arvind Halliyal, Minh Van Ngo, Mark T. Ramsbey, Hidehiko Shiraiwa +1 more | 2003-12-30 |
| 6667212 | Alignment system for planar charge trapping dielectric memory cell lithography | Hidehiko Shiraiwa, Kouros Ghandehari | 2003-12-23 |
| 6653191 | Memory manufacturing process using bitline rapid thermal anneal | Arvind Halliyal, Amir H. Jafarpour, Tazrien Kamal, Mark T. Ramsbey, Emmanuil Lingunis +1 more | 2003-11-25 |
| 6653190 | Flash memory with controlled wordline width | Kouros Ghandehari, Tazrien Kamal, Minh Van Ngo, Mark T. Ramsbey, Dawn Hopper +2 more | 2003-11-25 |
| 6627887 | System and method for constructing a profile of a structure in an integrated circuit | Ian Dudley, Paula Rao | 2003-09-30 |
| 6620717 | Memory with disposable ARC for wordline formation | Tazrien Kamal, Scott A. Bell, Kouros Ghandehari, Mark T. Ramsbey, Jeffrey A. Shields | 2003-09-16 |
| 6617215 | Memory wordline hard mask | Arvind Halliyal, Tazrien Kamal, Minh Van Ngo, Mark T. Ramsbey, Jeffrey A. Shields +3 more | 2003-09-09 |
| 6555436 | Simultaneous formation of charge storage and bitline to wordline isolation | Mark T. Ramsbey, Hidehiko Shiraiwa, Michael A. Van Buskirk, David Michael Rogers, Ravi Sunkavalli +3 more | 2003-04-29 |