Issued Patents All Time
Showing 26–50 of 51 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9391270 | Memory cells with vertically integrated tunnel access device and programmable impedance element | Jeffrey A. Shields, Yi Ma, Chakravarthy Gopalan, Ming Sung Kwon, John Dinh | 2016-07-12 |
| 9368198 | Circuits and methods for placing programmable impedance memory elements in high impedance states | Deepak Kamalanathan, Juan Pablo Saenz Echeverry | 2016-06-14 |
| 9368206 | Capacitor arrangements using a resistive switching memory cell structure | John Dinh, Ming Sang Kwan, Derric Lewis, Shane Hollmer, John Ross Jameson +1 more | 2016-06-14 |
| 9305643 | Solid electrolyte based memory devices and methods having adaptable read threshold levels | Foroozan Sarah Koushan, Derric Lewis | 2016-04-05 |
| 9025396 | Pre-conditioning circuits and methods for programmable impedance elements in memory devices | Foroozan Sarah Koushan, Deepak Kamalanathan, Juan Pablo Saenz Echeverry, Janet Wang | 2015-05-05 |
| 9007808 | Safeguarding data through an SMT process | John Dinh, Derric Lewis, Deepak Kamalanathan, Shane Hollmer, Juan Pablo Saenz Echeverry | 2015-04-14 |
| 8941089 | Resistive switching devices and methods of formation thereof | Chakravarthy Gopalan, Jeffrey A. Shields, Janet Wang, Kuei-Chang Tsai | 2015-01-27 |
| 8730752 | Circuits and methods for placing programmable impedance memory elements in high impedance states | Deepak Kamalanathan, Juan Pablo Saenz Echeverry | 2014-05-20 |
| 8099705 | Technique for determining circuit interdependencies | Paul J. Dickinson, Karl P. Dahlgren, Liang Chen | 2012-01-17 |
| 8021955 | Method characterizing materials for a trench isolation structure having low trench parasitic capacitance | Arvind Kamath, Mohammad Mirabedini, Ming-Yi Lee | 2011-09-20 |
| 7802217 | Leakage power optimization considering gate input activity and timing slack | Krishnan Sundaresan, Jaewon Oh, Ke-Ou Peng, Robert E. Mains | 2010-09-21 |
| 7679978 | Scheme for screening weak memory cell | Hua-Yu Su, Raymond A. Heald, Wen-Jay Hsu, Paul J. Dickinson, Lik T. Cheng +1 more | 2010-03-16 |
| 7619294 | Shallow trench isolation structure with low trench parasitic capacitance | Arvind Kamath, Mohammad Mirabedini, Ming-Yi Lee | 2009-11-17 |
| 7413996 | High k gate insulator removal | Arvind Kamath, Wai Lo | 2008-08-19 |
| 7189628 | Fabrication of trenches with multiple depths on the same substrate | Mohammad R. Mirbedini, Hong Lin, Verne Hornback, Dodd Defibaugh, Ynhi Le | 2007-03-13 |
| 7026217 | Method of forming an antifuse on a semiconductor substrate using wet oxidation of a nitrided substrate | Arvind Kamath, Wen-Chin Yeh, David William PACHURA | 2006-04-11 |
| 7001823 | Method of manufacturing a shallow trench isolation structure with low trench parasitic capacitance | Arvind Kamath, Mohammad Mirabedini, Ming-Yi Lee | 2006-02-21 |
| 6989331 | Hard mask removal | Arvind Kamath, Mohammad Mirabedini, Ming-Yi Lee, Brian A. Baylis | 2006-01-24 |
| 6864152 | Fabrication of trenches with multiple depths on the same substrate | Mohammad R. Mirbedini, Hong Lin, Verne Hornback, Dodd Defibaugh, Ynhi Le | 2005-03-08 |
| 6812158 | Modular growth of multiple gate oxides | Wen-Chin Yeh, Arvind Kamath | 2004-11-02 |
| 6734081 | Shallow trench isolation structure for laser thermal processing | Helmut Puchner | 2004-05-11 |
| 6614283 | Voltage level shifter | Peter J. Wright, Todd A. Randazzo | 2003-09-02 |
| 6586814 | Etch resistant shallow trench isolation in a semiconductor wafer | Rajiv Patel, David Chan, Arvind Kamath, Ken Rafftesaeth | 2003-07-01 |
| 6569739 | Method of reducing the effect of implantation damage to shallow trench isolation regions during the formation of variable thickness gate layers | Arvind Kamath | 2003-05-27 |
| 6566244 | Process for improving mechanical strength of layers of low k dielectric material | Charles E. May, Peter J. Wright | 2003-05-20 |