RP

Rajiv Patel

Lsi Logic: 7 patents #248 of 1,957Top 15%
📍 San Jose, CA: #8,424 of 32,062 inventorsTop 30%
🗺 California: #82,707 of 386,348 inventorsTop 25%
Overall (All Time): #757,154 of 4,157,543Top 20%
7
Patents All Time

Issued Patents All Time

Showing 1–7 of 7 patents

Patent #TitleCo-InventorsDate
6680243 Shallow junction formation Arvind Kamath 2004-01-20
6656805 METHOD OF REDUCING SILICON OXYNITRIDE GATE INSULATOR THICKNESS IN SOME TRANSISTORS OF A HYBRID INTEGRATED CIRCUIT TO OBTAIN INCREASED DIFFERENTIAL IN GATE INSULATOR THICKNESS WITH OTHER TRANSISTORS OF THE HYBRID CIRCUIT Arvind Kamath, Ravindra M. Kapre 2003-12-02
6586814 Etch resistant shallow trench isolation in a semiconductor wafer David Chan, Arvind Kamath, Ken Rafftesaeth, Venkatesh P. Gopinath 2003-07-01
6562729 Silicon nitride and silicon dioxide gate insulator transistors and method of forming same in a hybrid integrated circuit Arvind Kamath, Mohammad Mirabedini 2003-05-13
6521549 METHOD OF REDUCING SILICON OXYNITRIDE GATE INSULATOR THICKNESS IN SOME TRANSISTORS OF A HYBRID INTEGRATED CIRCUIT TO OBTAIN INCREASED DIFFERENTIAL IN GATE INSULATOR THICKNESS WITH OTHER TRANSISTORS OF THE HYBRID CIRCUIT Arvind Kamath, Ravindra M. Kapre 2003-02-18
6436845 Silicon nitride and silicon dioxide gate insulator transistors and method of forming same in a hybrid integrated circuit Arvind Kamath, Mohammad Mirabedini 2002-08-20
6335295 Flame-free wet oxidation 2002-01-01