Issued Patents All Time
Showing 1–22 of 22 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12183395 | Silicon-oxide-nitride-oxide-silicon based multi-level non-volatile memory device and methods of operation thereof | Venkatraman Prabhakar, Krishnaswamy Ramkumar, Vineet Agrawal, Long Hinh, Swatilekha Saha +2 more | 2024-12-31 |
| 11876090 | ESD protection circuit | David Michael Rogers, Eric N. Mann, Eric Lee Swindlehurst, Toru Miyamae, Timothy Williams +6 more | 2024-01-16 |
| 11810616 | Silicon-oxide-nitride-oxide-silicon multi-level non-volatile memory device and methods of fabrication thereof | Krishnaswamy Ramkumar, Venkatraman Prabhakar, Vineet Agrawal, Long Hinh, Santanu Kumar Samanta | 2023-11-07 |
| 11581729 | Combined positive and negative voltage electrostatic discharge (ESD) protection clamp with cascoded circuitry | David Michael Rogers, Henry H. Yuan, Mimi Qian, Myeongseok Lee, Sungkwon Lee +2 more | 2023-02-14 |
| 11521962 | ESD protection circuit | David Michael Rogers, Eric N. Mann, Eric Lee Swindlehurst, Toru Miyamae, Timothy Williams +6 more | 2022-12-06 |
| 11367481 | Silicon-oxide-nitride-oxide-silicon based multi-level non-volatile memory device and methods of operation thereof | Venkataraman Prabhakar, Krishnaswamy Ramkumar, Vineet Agrawal, Long Hinh, Swatilekha Saha +2 more | 2022-06-21 |
| 11355185 | Silicon-oxide-nitride-oxide-silicon multi-level non-volatile memory device and methods of fabrication thereof | Krishnaswamy Ramkumar, Venkatraman Prabhakar, Vineet Agrawal, Long Hinh, Santanu Kumar Samanta | 2022-06-07 |
| 11017851 | Silicon-oxide-nitride-oxide-silicon based multi level non-volatile memory device and methods of operation thereof | Venkataraman Prabhakar, Krishnaswamy Ramkumar, Vineet Agrawal, Long Hinh, Swatilekha Saha +2 more | 2021-05-25 |
| 9842629 | Memory cell array latchup prevention | Shahin Sharifzadeh, Helmut Puchner, Nayan Patel | 2017-12-12 |
| 8493804 | Memory cell array latchup prevention | Shahin Sharifzadeh | 2013-07-23 |
| 8252640 | Polycrystalline silicon activation RTA | Sethuraman Lakshminarayanan | 2012-08-28 |
| 8143129 | Integration of non-volatile charge trap memory devices and logic CMOS devices | Krishnaswamy Ramkumar, Jeremy B. Warren | 2012-03-27 |
| 8093128 | Integration of non-volatile charge trap memory devices and logic CMOS devices | William Koutny, Sam Geha, Igor G. Kouznetsov, Krishnaswamy Ramkumar, Fredrick B. Jenne +2 more | 2012-01-10 |
| 8045410 | Memory cell array | Shahin Sharifzadeh | 2011-10-25 |
| 7773442 | Memory cell array latchup prevention | Shahin Sharifzadeh | 2010-08-10 |
| 7629653 | Techniques for improving negative bias temperature instability (NBTI) lifetime of field effect transistors | Sharmin Sadoughi, Krishnaswamy Ramkumar, Igor Polishchuk, Maroun Georges Khoury | 2009-12-08 |
| 7256087 | Techniques for improving negative bias temperature instability (NBTI) lifetime of field effect transistors | Sharmin Sadoughi, Krishnaswamy Ramkumar, Igor Polishchuk, Maroun Georges Khoury | 2007-08-14 |
| 6759337 | Process for etching a controllable thickness of oxide on an integrated circuit structure on a semiconductor substrate using nitrogen plasma and plasma and an rf bias applied to the substrate | Sheldon Aronowitz, Valeriy Sukharev, John Haywood, James Kimball, Helmut Puchner +1 more | 2004-07-06 |
| 6747318 | Buried channel devices and a process for their fabrication simultaneously with surface channel devices to produce transistors and capacitors with multiple electrical gate oxides | Tommy Hsiao, Yanhua Wang, Kyungjin Min | 2004-06-08 |
| 6656805 | METHOD OF REDUCING SILICON OXYNITRIDE GATE INSULATOR THICKNESS IN SOME TRANSISTORS OF A HYBRID INTEGRATED CIRCUIT TO OBTAIN INCREASED DIFFERENTIAL IN GATE INSULATOR THICKNESS WITH OTHER TRANSISTORS OF THE HYBRID CIRCUIT | Arvind Kamath, Rajiv Patel | 2003-12-02 |
| 6521549 | METHOD OF REDUCING SILICON OXYNITRIDE GATE INSULATOR THICKNESS IN SOME TRANSISTORS OF A HYBRID INTEGRATED CIRCUIT TO OBTAIN INCREASED DIFFERENTIAL IN GATE INSULATOR THICKNESS WITH OTHER TRANSISTORS OF THE HYBRID CIRCUIT | Arvind Kamath, Rajiv Patel | 2003-02-18 |
| 6413881 | PROCESS FOR FORMING THIN GATE OXIDE WITH ENHANCED RELIABILITY BY NITRIDATION OF UPPER SURFACE OF GATE OF OXIDE TO FORM BARRIER OF NITROGEN ATOMS IN UPPER SURFACE REGION OF GATE OXIDE, AND RESULTING PRODUCT | Sheldon Aronowitz, John Haywood, James Kimball, Helmut Puchner, Nicholas K. Eib | 2002-07-02 |