JK

James Kimball

Lsi Logic: 19 patents #62 of 1,957Top 4%
Overall (All Time): #241,581 of 4,157,543Top 6%
19
Patents All Time

Issued Patents All Time

Patent #TitleCo-InventorsDate
7323228 Method of vaporizing and ionizing metals for use in semiconductor processing Sheldon Aronowitz 2008-01-29
7084408 Vaporization and ionization of metals for use in semiconductor processing Sheldon Aronowitz 2006-08-01
6864141 Method of incorporating nitrogen into metal silicate based dielectrics by energized nitrogen ion beams Wai Lo, Verne Hornback 2005-03-08
6849512 Thin gate dielectric for a CMOS transistor and method of fabrication thereof Wai Lo, Verne Hornback 2005-02-01
6759337 Process for etching a controllable thickness of oxide on an integrated circuit structure on a semiconductor substrate using nitrogen plasma and plasma and an rf bias applied to the substrate Sheldon Aronowitz, Valeriy Sukharev, John Haywood, Helmut Puchner, Ravindra M. Kapre +1 more 2004-07-06
6413881 PROCESS FOR FORMING THIN GATE OXIDE WITH ENHANCED RELIABILITY BY NITRIDATION OF UPPER SURFACE OF GATE OF OXIDE TO FORM BARRIER OF NITROGEN ATOMS IN UPPER SURFACE REGION OF GATE OXIDE, AND RESULTING PRODUCT Sheldon Aronowitz, John Haywood, Helmut Puchner, Ravindra M. Kapre, Nicholas K. Eib 2002-07-02
6331468 Formation of integrated circuit structure using one or more silicon layers for implantation and out-diffusion in formation of defect-free source/drain regions and also for subsequent formation of silicon nitride spacers Sheldon Aronowitz, Helmut Puchner, Ravindra Kapre 2001-12-18
6180470 FETs having lightly doped drain regions that are shaped with counter and noncounter dorant elements Sheldon Aronowitz, Laique Khan 2001-01-30
6087229 Composite semiconductor gate dielectrics Sheldon Aronowitz, David Chan, David Lee, John Haywood, Valeriy Sukharev 2000-07-11
6060375 Process for forming re-entrant geometry for gate electrode of integrated circuit structure Jon S. Owyang, Sheldon Aronowitz 2000-05-09
6033998 Method of forming variable thickness gate dielectrics Sheldon Aronowitz, David Chan, David Lee, John Haywood, Valeriy Sukharev 2000-03-07
5963801 Method of forming retrograde well structures and punch-through barriers using low energy implants Sheldon Aronowitz, Laique Khan 1999-10-05
5904551 Process for low energy implantation of semiconductor substrate using channeling to form retrograde wells Sheldon Aronowitz 1999-05-18
5858864 Process for making group IV semiconductor substrate treated with one or more group IV elements to form barrier region capable of inhibiting migration of dopant materials in substrate Sheldon Aronowitz 1999-01-12
5739580 Oxide formed in semiconductor substrate by implantation of substrate with a noble gas prior to oxidation Sheldon Aronowitz 1998-04-14
5717238 Substrate with controlled amount of noble gas ions to reduce channeling and/or diffusion of a boron dopant forming P-LDD region of a PMOS device Sheldon Aronowitz, Yu-Lam Ho, Gobi R. Padmanabhan, Douglas T. Grider, Chi-Yi Kao 1998-02-10
5707888 Oxide formed in semiconductor substrate by implantation of substrate with a noble gas prior to oxidation Sheldon Aronowitz 1998-01-13
5654210 Process for making group IV semiconductor substrate treated with one or more group IV elements to form one or more barrier regions capable of inhibiting migration of dopant materials in substrate Sheldon Aronowitz 1997-08-05
5585286 Implantation of a semiconductor substrate with controlled amount of noble gas ions to reduce channeling and/or diffusion of a boron dopant subsequently implanted into the substrate to form P- LDD region of a PMOS device Sheldon Aronowitz, Yu-Lam Ho, Gobi R. Padmanabhan, Douglas T. Grider, Chi-Yi Kao 1996-12-17