GP

Gobi R. Padmanabhan

NS National Semiconductor: 22 patents #55 of 2,238Top 3%
Lsi Logic: 17 patents #73 of 1,957Top 4%
TI Texas Instruments: 1 patents #7,357 of 12,488Top 60%
📍 Sunnyvale, CA: #487 of 14,302 inventorsTop 4%
🗺 California: #11,329 of 386,348 inventorsTop 3%
Overall (All Time): #80,098 of 4,157,543Top 2%
40
Patents All Time

Issued Patents All Time

Showing 1–25 of 40 patents

Patent #TitleCo-InventorsDate
8288834 Semiconductor wafer and die that include an integrated circuit and two or more different MEMS-based semiconductor devices Visvamohan Yegnashankaran 2012-10-16
7790602 Method of forming a metal interconnect with capacitive structures that adjust the capacitance of the interconnect Visvamohan Yegnashankaran 2010-09-07
7633131 MEMS semiconductor sensor device Visvamohan Yegnashankaran 2009-12-15
7482228 Method of forming a MOS transistor with a litho-less gate Visvamohan Yegnashankaran 2009-01-27
7399274 Sensor configuration for a capsule endoscope Brian L. Halla, Joseph D. Montalbo, Peter Yi-Ning Wang 2008-07-15
7338840 Method of forming a semiconductor die with heat and electrical pipes Visvamohan Yegnashankaran 2008-03-04
7329555 Method of selectively forming MEMS-based semiconductor devices at the end of a common fabrication process Visvamohan Yegnashankaran 2008-02-12
7230301 Single-crystal silicon semiconductor structure Visvamohan Yegnashankaran 2007-06-12
7192819 Semiconductor sensor device using MEMS technology Visvamohan Yegnashankaran 2007-03-20
7109571 Method of forming a hermetic seal for silicon die with metal feed through structure Visvamohan Yegnashankaran 2006-09-19
7075133 Semiconductor die with heat and electrical pipes Visvamohan Yegnashankaran 2006-07-11
7052977 Method of dicing a semiconductor wafer that substantially reduces the width of the saw street Visvamohan Yegnashankaran 2006-05-30
7044908 Method and system for dynamically adjusting field of view in a capsule endoscope Joseph D. Montalbo 2006-05-16
7042092 Multilevel metal interconnect and method of forming the interconnect with capacitive structures that adjust the capacitance of the interconnect Visvamohan Yegnashankaran 2006-05-09
6949421 Method of forming a vertical MOS transistor Visvamohan Yegnashankaran 2005-09-27
6946321 Method of forming the integrated circuit having a die with high Q inductors and capacitors attached to a die with a circuit as a flip chip Visvamohan Yegnashankaran 2005-09-20
6833781 High Q inductor in multi-level interconnect Visvamohan Yegnashankaran 2004-12-21
6781239 Integrated circuit and method of forming the integrated circuit having a die with high Q inductors and capacitors attached to a die with a circuit as a flip chip Visvamohan Yegnashankaran 2004-08-24
6777288 Vertical MOS transistor Visvamohan Yegnashankaran 2004-08-17
6746956 Hermetic seal for silicon die with metal feed through structure Visvamohan Yegnashankaran 2004-06-08
6730969 Radiation hardened MOS transistor Visvamohan Yegnashankaran, Reda R. Razouk 2004-05-04
6723593 Deep submicron MOS transistor with increased threshold voltage Visvamohan Yegnashankaran, Reda R. Razouk 2004-04-20
6677235 Silicon die with metal feed through structure Visvamohan Yegnashankaran 2004-01-13
5917207 Programmable polysilicon gate array base cell architecture Michael J. Colwell, Teh-Kuin Lee, Jane C.T. Chiu, Abraham Yee, Stanley Yeh 1999-06-29
5874754 Microelectronic cells with bent gates and compressed minimum spacings, and method of patterning interconnections for the gates Jasopin Lee, Abraham Yee, Stanley Yeh 1999-02-23